Tech Forum, February 5, features 32/28-, 20-, 14-, and 10-nanometer processes

Tech Forum, February 5, features 32/28-, 20-, 14-, and 10-nanometer processes
by Daniel Nenni on 01-04-2013 at 7:00 pm

The Common Platform Alliance — IBM, Samsung Electronics, Co., Ltd., and GLOBALFOUNDRIES — continues to redefine the landscape of the semiconductor industry with its groundbreaking collaboration. Join us at our 2013 Common Platform Technology Forumon Tuesday, February 5, 2013 at the Santa Clara Convention Center as we showcaseRead More


HiFi Mini, Always Listening

HiFi Mini, Always Listening
by Paul McLellan on 01-03-2013 at 10:28 am

Next week it is the Consumer Electronics Show (CES) in Las Vegas and so there are announcements around the areas where consumer overlaps with semiconductor, which these days is primarily mobile. Then in February in Barcelona is Mobile World Congress, which is even more focused on mobile. Expect more announcementst there.

Currently… Read More


Wafer Costs: Out of Control or Not?

Wafer Costs: Out of Control or Not?
by Paul McLellan on 01-01-2013 at 8:30 pm

I didn’t attend the International Electronic Device Meeting (IEDM) earlier this month, but there have been a lot of reports on the inter webs especially about 20nm and 14nm processes. Some of this is really geeky stuff but I think that perhaps the most interesting thing I’ve read about is summarized in this chart:

This… Read More


Cadence 3D Methodology

Cadence 3D Methodology
by Paul McLellan on 12-28-2012 at 8:20 pm

A couple of weeks ago was the 3D Architectures for Semiconductor Integration and Packagingconference in Redwood City. Cadence presented the changes that they have been making to their tool flow to enabled 2.5D (interposer-based) and true 3D TSV-based designs. You know what TSV stands for by now right? Through-silicon-via, … Read More


Equipment Down 16% in 2012, Flat to Down in 2013

Equipment Down 16% in 2012, Flat to Down in 2013
by Bill Jewell on 12-22-2012 at 8:30 pm

Shipments of semiconductor manufacturing equipment have been trending downward since June 2012, based on combined data from SEMI for North American and European manufacturers and from SEAJ for Japanese manufacturers. The market bounced back strongly in late 2009 and in 2010 after the 2008 downturn to return to the $3 billionRead More


Formal Verification at ARM

Formal Verification at ARM
by Paul McLellan on 12-20-2012 at 4:34 pm

There are two primary microprocessor companies in the world these days: Intel and ARM. Of course there are many others but Intel is dominant on the PC desktop (including Macs) and ARM is dominant in mobile (including tablets).

One of the keynotes at last month’s Jasper User Group (JUG, not the greatest of acronyms) was by Bob… Read More


IP Scoring Using TSMC DFM Kits

IP Scoring Using TSMC DFM Kits
by Daniel Payne on 12-20-2012 at 11:00 am

Design For Manufacturing (DFM) is the art and science of making an IC design yield better in order to receive a higher ROI. Ian Smith, an AE from Mentor in the Calibre group presented a pertinent webinar, IP Scoring Using TSMC DFM Kits. I’ll provide an overview of what I learned at this webinar.… Read More


A Brief History of Berkeley Design Automation

A Brief History of Berkeley Design Automation
by Daniel Nenni on 12-18-2012 at 1:00 pm

Analog, mixed-signal, RF, and custom digital circuitry implemented in GHz nanometer CMOS introduce a new class of design and verification challenges that traditional transistor‑level simulators cannot adequately address. Berkeley Design Automation, Inc., (BDA) was founded in 2003 by Amit Mehrotra and Amit Narayan,… Read More


Double Patterning Tutorial

Double Patterning Tutorial
by Paul McLellan on 12-17-2012 at 4:07 am

Double patterning at 20nm is one of those big unavoidable changes that it is almost impossible to know too much about. Mentor’s David Abercrombie, DFM Program Manager for Calibre, has written a series of articles detailing the multifaceted impacts of double patterning on advanced node design and verification. There is… Read More


Apache/Ansys presents: 3DIC thermal, transmission lines, low frequency analysis

Apache/Ansys presents: 3DIC thermal, transmission lines, low frequency analysis
by Paul McLellan on 12-16-2012 at 10:00 pm

Late in January it is DesignCon at the Santa Clara convention center from January 28th-31st. Details are here.

On Tuesday from 11.05 to 11.45 Apache and Ansys will be presenting on Thermal Co-analysis of 3D IC/packages/system. This is being presented by a whole team of people: Stephen Pan, senior product specialist at ANSYS; Norman… Read More