KLAC & LRCX – Fall Out from the deal Falling Apart (1 of 3)

KLAC & LRCX – Fall Out from the deal Falling Apart (1 of 3)
by Robert Maire on 10-09-2016 at 7:00 am

The odds of deal completion has fallen to low levels. Whats the fallout on the companies and stocks? Is there life after a failed merger?

“A quagmire wrapped up inside an enigma” – LRCX & KLAC’s merger is the talk of the town, both in the semiconductor equipment industry as well as DOJ watchers in Washington… Read More


GLOBALFOUNDRIES Extends the FDSOI Roadmap

GLOBALFOUNDRIES Extends the FDSOI Roadmap
by Scotten Jones on 09-19-2016 at 12:00 pm

On September 8, 2016 GLOBALFOUNDRIES (GF) announced their 12nm FDSOI technology node. On September 12th I had a chance to interview Greg Bartlett, GF Senior Vice President for the CMOS Business Unit (as a side note, GF has: RF SOI, ASIC and CMOS business units).… Read More


CEO Interview: Xerxes Wania of Sidense

CEO Interview: Xerxes Wania of Sidense
by Daniel Nenni on 09-19-2016 at 7:00 am

This is the first in a series of CEO interviews and I thought semiconductor IP would be a great place to start. Xerxes Wania is the President and CEO of Sidense, a leading developer of Non-Volatile Memory (NVM) One-Time Programmable (OTP) IP cores. Sidense has been a part of SemiWiki since 2013 so we know them quite well. I hope the rest… Read More


KLAM Kommentary – Assessing the political landscape of approval

KLAM Kommentary – Assessing the political landscape of approval
by Robert Maire on 09-16-2016 at 12:00 pm

LRCX & KLAC’s merger continues to be closely watched given the recent turns and reversals we have seen which call into question the ability to get the deal done. The deal was announced in October of 2015 and we are on our second request from the DOJ and the deal will almost certainly go beyond the Oct 20th, one year deadlineRead More


Market Trends Motivate a Shift-Left in Functional Verification

Market Trends Motivate a Shift-Left in Functional Verification
by Jean-Marie Brunet on 09-15-2016 at 4:00 pm

Today, in the context of functional verification, industry trends are based on the needs of prominent vertical markets. There is some overlap in what these markets need, but there are some use models that are very specific to each market.

We assert this because we have a lot of customers asking about emulation solutions not from … Read More


GlobalFoundries Roadmap Update 2016!

GlobalFoundries Roadmap Update 2016!
by Daniel Nenni on 09-15-2016 at 11:00 am

I attended a lunch yesterday with GlobalFoundries CEO Sanjay Jha (formerly of Qualcomm), SVP Gregg Barltlett (Motorola/GF), and CTO Gary Patton (IBM). Having followed GF from the very beginning I can tell you without a shadow of a doubt that GF has transformed from a collection of companies (AMD, Chartered, IBM) to a fully integrated… Read More


A new world of 10nm design constraints

A new world of 10nm design constraints
by Beth Martin on 08-30-2016 at 4:00 pm

Every time the industry transitions to a smaller process node IC design software undergoes extensive updates.

I talked to a couple of experts in physical design at Mentor Graphics about what is involved in making place-and-route software ready for a new node. This is what I learned from Sudhakar Jilla, the IC design marketing director… Read More


Further delays in KLAM deal not a good omen

Further delays in KLAM deal not a good omen
by Robert Maire on 08-14-2016 at 4:00 pm

Deal likely getting worse as time & remedies go by…
Just a couple of short weeks ago on the earnings conference call, Lam management was adamant about the KLAM deal getting done and done by the Oct 20th deadline. Martin Anstice, the CEO , went to great lengths to tell us that the deal was under control, was going to happen,
Read More


STT-MRAM – Coming soon to an SoC near you

STT-MRAM – Coming soon to an SoC near you
by Tom Dillinger on 07-05-2016 at 4:00 pm

An increasing percentage of SoC die area is being allocated to memory arrays, as applications require more data/instruction storage and boot firmware. Indeed, foundries invest considerable R&D resources into optimizing their array technology IP offerings, often with more aggressive device features than used for other… Read More


CEO Insight: Transformation of Vayavya Labs into System Design Automation

CEO Insight: Transformation of Vayavya Labs into System Design Automation
by Pawan Fangaria on 05-12-2016 at 7:00 am

With the advent of SoCs, design abstractions and verification has moved up at the system level. It’s imperative that EDA moves up the value chain to start design automation at system level. The System Design Automation will be the new face of EDA in coming years.… Read More