A Six-Minute Journey to Secure Chip Design with Caspia

A Six-Minute Journey to Secure Chip Design with Caspia
by Mike Gianfagna on 11-11-2025 at 6:00 am

A Six Minute Journey to Secure Hardware Design with Caspia

Hardware-level chip security has become an important topic across the semiconductor ecosystem. Thanks to sophisticated AI-fueled attacks, the hardware root of trust and its firmware are now vulnerable. And unlike software security, an instantiated weakness cannot be patched. The implications of such vulnerabilities are… Read More


Think Quantum Computing is Hype? Mastercard Begs to Disagree

Think Quantum Computing is Hype? Mastercard Begs to Disagree
by Bernard Murphy on 11-10-2025 at 6:00 am

Just got an opportunity to write a blog on PQShield, and I’m delighted for several reasons. Happy to work with a company based in Oxford and happy to work on a quantum computing-related topic, which you’ll find I will be getting into more deeply over coming months. (Need a little relief from a constant stream of AI topics.) Also important,… Read More


Moores Lab(AI): Agentic AI and the New Era of Semiconductor Design

Moores Lab(AI): Agentic AI and the New Era of Semiconductor Design
by Kalar Rajendiran on 10-08-2025 at 10:00 am

Silicon Engineering at the Speed of AI

For decades, chip design has been a delicate balance of creativity and drudgery. Architects craft detailed specifications, engineers read those documents line by line, and teams write and debug thousands of lines of Verilog and UVM code. Verification alone can consume up to 35 percent of a project’s cost and add many months to … Read More


Prompt Engineering for Security: Innovation in Verification

Prompt Engineering for Security: Innovation in Verification
by Bernard Murphy on 07-30-2025 at 6:00 am

Innovation New

We have a shortage of reference designs to test detection of security vulnerabilities. An LLM-based method demonstrates how to fix that problem with structured prompt engineering. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford,… Read More


Hardwear.io Security Trainings and Conference Netherlands 2025

Hardwear.io Security Trainings and Conference Netherlands 2025
by Admin on 06-10-2025 at 4:58 pm

The Netherlands has been the home for Hardwear.io since 2015.

We are very excited to host the industry from automotive, healthcare, semiconductor, IoT, industrial control systems and Govt/Defences Institutes to join us for Hardwear.io NL scheduled on 17th Nov to 21st Nov 2025 at Amsterdam Marriott Hotel

Learn, share, build,… Read More


MCUs Are Now Embracing Mainstream NoCs

MCUs Are Now Embracing Mainstream NoCs
by Bernard Murphy on 01-16-2025 at 6:00 am

MCU applications

The moral of today’s story is that to succeed in a late-adopter market, sometimes you just have to wait for the market to catch up (assuming you have a strong early adopter market to buy your product today). I have been working with Arteris for 6+ years now promoting their NoC technology, and there was never any question that they offer… Read More


Overcoming obstacles with mixed-signal and analog design integration

Overcoming obstacles with mixed-signal and analog design integration
by Chris Morrison on 10-28-2024 at 10:00 am

Central,Computer,Processors,Cpu,Concept.,3d,Rendering,conceptual,Image.

Mixed-signal and analog design are key aspects of modern electronics. Every chip incorporates some form of analog IP, as even digital logic is dependent on analog signals for critical functions. Many digital design engineers are known to be uncomfortable with the prospect of integrating analog components. However, the current… Read More


Synopsys Design IP for Modern SoCs and Multi-Die Systems

Synopsys Design IP for Modern SoCs and Multi-Die Systems
by Kalar Rajendiran on 04-11-2024 at 10:00 am

Synopsys IP Scale, a Sustainable Advantage

Semiconductor intellectual property (IP) plays a critical role in modern system-on-chip (SoC) designs. That’s not surprising given that modern SoCs are highly complex designs that leverage already proven building blocks such as processors, interfaces, foundational IP, on-chip bus fabrics, security IP, and others. This… Read More


ESD Alliance and Silicon Assurance Host Industry Panel Discussion on Chiplet Security

ESD Alliance and Silicon Assurance Host Industry Panel Discussion on Chiplet Security
by Bob Smith on 02-13-2024 at 6:00 am

Phishing,,E mail,,Network,Security,,Computer,Hacker,,Cloud,Computing,Cyber,Security

Security threats are a hot topic of discussion today as they can have a profound impact on the electronic infrastructure and devices that are the backbone of our global economies. It is also clear that these threats can be introduced during the design of the very devices that we rely on in our daily lives.

Chiplet-based design is … Read More


Securing Memory Interfaces

Securing Memory Interfaces
by Kalar Rajendiran on 03-30-2023 at 10:00 am

synopsys secure ddr controller with ime

News of hackers breaking into systems is becoming common place these days. While many of the breaches reported to date may have been due to security flaws in software, vulnerabilities exist in hardware too. As a result, the topic of security is getting increased attention within the semiconductor industry around system-on-chip… Read More