SEMICON West Intel 10nm and GF 7nm Update

SEMICON West Intel 10nm and GF 7nm Update
by Daniel Nenni on 07-18-2018 at 7:00 am

SEMICON West seemed a little slow last week but maybe it was just me. I’m sure SEMI will come out with record breaking numbers but I did not see it in the exhibit hall (see the video). What I did see was hundreds of exhibitors but I had no idea what they did. San Francisco again was very congested and smelly. I talked to a friend who is in public… Read More


Imec technology forum 2018 – the future of memory

Imec technology forum 2018 – the future of memory
by Scotten Jones on 06-05-2018 at 12:00 pm

At the Imec technology forum in Belgium Gouri Sankar Kar and Arnaud Furnemont presented memory and storage perspectives and I also got to interview Arnaud. Arnaud leads overall memory development at Imec and personally leads NAND and DNA research.

Memory research is focused on power, energy, speed and cost with energy and throughput… Read More


imec and Cadence on 3nm

imec and Cadence on 3nm
by Daniel Nenni on 04-30-2018 at 7:00 am

One of the more frequent questions I get, “What is next after FinFETs?” is finally getting answered. Thankfully I am surrounded by experts in the process technology field including Scotten Jones of IC Knowledge. I am also surrounded by design enablement experts so I really am the man in the middle which brings us to a discussion between… Read More


Samsung is Starting 7nm Production with EUV in June

Samsung is Starting 7nm Production with EUV in June
by Scotten Jones on 04-16-2018 at 12:00 pm

There is a report in the Seoul Economic Daily that Samsung has completed development of their 7nm process using EUV and that production will begin in June. What is claimed in the report is:

  • The process is installed in the Hwaseong S3 Fab
  • Samsung has more than 10 EUV systems installed
  • Production starts in June with Qualcomm, Xilinx,
Read More

IEDM 2017 Preview

IEDM 2017 Preview
by Scotten Jones on 10-20-2017 at 7:00 am

The 63rd annual IEDM (International Electron Devices Meeting) will be held December 2nd through 6th in San Francisco. In my opinion IEDM is one of, if not the premier conference on leading edge semiconductor technology. I will be attending the conference again this year and providing coverage for SemiWiki. As a member of the press… Read More


SEMICON West – EUV Readiness Update

SEMICON West – EUV Readiness Update
by Scotten Jones on 08-11-2017 at 12:00 pm

At the imec technology forum held at SEMICON West, Martin Van Den Brink, President and CTO of ASML presented on the latest developments on EUV. I also had an opportunity to sit down with Mike Lercel, ASML Director of Strategic Marketing for an interview.… Read More


Standard Node Trend

Standard Node Trend
by Scotten Jones on 07-15-2017 at 4:00 pm

I have previously published analysis’ converting leading edge logic processes to “standard nodes” and comparing standard nodes by company and time. Recently updated details on the 7nm process node have become available and in this article, I will revisit the standard node calculations and trends.… Read More


3D NAND Myths and Realities

3D NAND Myths and Realities
by Scotten Jones on 06-30-2017 at 9:00 am

For many year 2D NAND drove lithography for the semiconductor industry with the smallest printed dimensions and yearly shrinks. As 2D NAND shrunk down to the mid-teens nodes, 16nm, 15nm and even 14nm, the cells became so small that there were only a few electrons in each cell and cross-talk issues made further shrinks very difficult… Read More


SPIE 2017 – imec papers and interview

SPIE 2017 – imec papers and interview
by Scotten Jones on 04-28-2017 at 12:00 pm

At the SPIE Advanced Lithography Conference imec published a number of papers on EUV, multi-patterning and other lithography issues. In addition to seeing several of the papers presented I had a chance to sit down with imec’s director of advanced patterning, Greg McIntyre. In this article I will summarize my discussions… Read More


SPIE 2017 ASML and Cadence EUV impact on place and route

SPIE 2017 ASML and Cadence EUV impact on place and route
by Scotten Jones on 04-13-2017 at 7:00 am

As feature sizes have shrunk, the semiconductor industry has moved from simple, single-exposure lithography solutions to increasingly complex resolution-enhancement techniques and multi-patterning. Where the design on a mask once matched the image that would be produced on the wafer, today the mask and resulting image … Read More