Silicon Catalyst Webinar: SiFive Maximizes Compute Density With Its RISC-V

Silicon Catalyst Webinar: SiFive Maximizes Compute Density With Its RISC-V
by Admin on 05-22-2023 at 2:31 pm

About this event

  • 1 hour
  • Mobile eTicket

IP vendor SiFive has been at the forefront of RISC-V’s rapidly growing adoption across a wide array of markets and applications. In this joint presentation with Ansys, SiFive will describe how achieving maximum compute density – compute horsepower per mm2 and per mW (e.g SPECint2006/mm2)

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Webinar: Don’t Take the Risk, Formally Verify Your RISC-V Cores

Webinar: Don’t Take the Risk, Formally Verify Your RISC-V Cores
by Admin on 05-16-2023 at 1:56 pm

Synopsys Webinar | Thursday, May 25, 2023 | 9:00 a.m. PT

According to a recent Semico Research report, the RISC-V Core IP market is expected to grow at a 34.9% CAGR through year 2027. With increasing popularity, it is of utmost importance that the RISC-V Core IPs are secure and bug free. ​

In this joint Synopsys webinar with SyoSil,

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Podcast EP157: The Differentiated Role Andes Plays in the US with Charlie Cheng

Podcast EP157: The Differentiated Role Andes Plays in the US with Charlie Cheng
by Daniel Nenni on 04-26-2023 at 10:00 am

Dan is joined by Charlie Cheng, Managing Director of Polyhedron. Prior to that, Charlie was the CEO of Kilopass Technology, where he grew the core memory business into a successful acquisition by Synopsys. Before that, Charlie was an Entrepreneur in Residence at US Venture Partners and a Corporate VP at Faraday Technology, a Taiwanese… Read More


Maven Silicon’s RISC-V Processor IP Verification Flow

Maven Silicon’s RISC-V Processor IP Verification Flow
by Sivakumar PR on 02-24-2023 at 6:00 am

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RISC-V is a general-purpose license-free open Instruction Set Architecture [ISA] with multiple extensions. It is an ISA separated into a small base integer ISA, usable as a base for customized accelerators and optional standard extensions to support general-purpose software development. RISC-V supports both 32-bit and … Read More


Webinar: Removing the Risk from RISC-V using the RISC-V Trace Standard

Webinar: Removing the Risk from RISC-V using the RISC-V Trace Standard
by Admin on 12-30-2022 at 11:51 am

With the growing maturity of the RISC-V ISA, chip companies now have a wealth of options for implementing RISC-V cores in their latest product. At the same time the support ecosystem is growing, with standards now defined for support technologies such as processor trace, which gives developers access to critical insights and

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CHIPS Alliance, Fall Technology Update

CHIPS Alliance, Fall Technology Update
by Admin on 12-14-2022 at 1:43 pm

SUNNYVALE, CA + VIRTUAL

Join us in-person for our second biannual technology update featuring informative, technical talks on open source hardware collaborative development, hosted by Google and including speakers from Microsoft, Google, Intel, Antmicro, Efabless and others.

CHIPS’ Thursday event follows the main RISC-V

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VeriSilicon’s VeriHealth Chip Design Platform for Smart Healthcare Applications

VeriSilicon’s VeriHealth Chip Design Platform for Smart Healthcare Applications
by Kalar Rajendiran on 12-13-2022 at 10:00 am

VeriHealth Showing Fall Detection

The wearables electronics market is a large and fast growing one. According to Precedence Research, the global wearable technology market is expected to grow at a compound annual growth rate of 13.89% during the forecast period 2022 to 2030. Precedence estimated the global wearable technology market size at USD 121.7 billion… Read More