You probably have seen many times this graphic showing that the number of IP blocks has exploded, going from a few dozens in SoC designed in 65 nm to 120 if not more for last generation SoC targeting 16FF or 10FF. This graphic is very good at synthesizing the raw IP count, but it doesn’t tell you about another strong trend: more agents … Read More
Tag: noc
How to Overcome NoC Validation Multiple Challenges?
NetSpeed has developed NocStudio, a front end optimization design tool helping architects to create SoC architecture bridging the gap with the back end, floor planning and place and route. At the chip level, NocStudio generates a cache-coherent Network-on-Chip (NoC) allowing interconnecting the various CPU, GPU or Acceleration… Read More
Why Modern SoC need cache-coherent NoC?
Launching high technology product on the semiconductor market after your competitors is not necessarily a weakness. NetSpeed has developed NocStudio, a front end optimization design tool helping architects to create SoC architecture bridging the gap with the back end, floor planning and place and route. Created about 20 years… Read More
NetSpeed NoC IP or Architectural Synthesis Company?
When you look at NetSpeed’s NocStudio design tool, you first think “I see, NetSpeed is a new Network-on-Chip (NoC) IP company”. Are you wrong? Yes and no… No because NocStudio indeed generates a NoC. Yes, because the company objectives are going much farther than simply deliver a new NoC solution. According with Sundari Mitra, … Read More
Opportunity NoCs, But Not Without Software
It is easy to think that semiconductor IP is all about structures on the silicon. After all, there is “semiconductor” in the phrase “semiconductor IP”. But increasingly the heart is actually software. Sonics’ SGN product is a network-on-chip but to build it you need to use the software that actually… Read More
Is Interconnect Ready for the Post-mobile SoCs?
The interconnect technology is one of the unsung heroes of the system-on-chip (SoC) revolution. It’s the on-chip networking fabric that is used to link various IP cores on an SoC floorplan. The technology facilitates links between multiple processors, on-chip memories, hardware accelerators and more. In other words,… Read More
Sonics’ New NoC
Today Sonics announced the latest version of their network-on-chip (NoC) technology, SonicsGN-3.0. As with any new release there are lots of improvements that are of interest mainly to existing users, but the big area with increased capability is the expanded interleaved memory technology (IMT). This was first introduced … Read More
SemiWiki at #52DAC: Nominated for Best Paper Award!
Blogging for Semiwiki is a very good exercise to prepare a paper submission at DAC. Writing a short article using about 600 words to pass one message, and try to deliver this message as clearly as possible. Writing a paper for DAC is very similar, as you have to be synthetic and develop a thesis in 5 slides, no more, as it’s a time limited… Read More
Is Low Power a Challenge? ICE-Grain Answers the Challenge
Blogs have limited wordcount so insert your own generic opening paragraph here about the importance of low power in IC design. Mention IoT and cloud datacenters for extra credit.
It is well-known that the biggest reductions in power come from changes at the architectural level. Tools and process can do some things and since they… Read More
Rockchip Bets on Arteris FlexNoC Interconnect IP to Leapfrog SoC Design
China was a virgin territory for Arteris Inc. before July 19, 2012 when Fuzhou Rockchip Electronics announced that it has licensed the Arteris FlexNoC network-on-chip (NoC)-based interconnect IP technology for its multicore SoCs for budget Android tablets. Rockchip mostly targets the tablet and set-top box (STB) markets … Read More