Axiomise has recently launched a new verification tool called nocProve which will transform how Network-on-Chip designs are validated in modern hardware development, absolutely.
The tool is designed to be the first configurable formal verification application specifically created for NoC implementations. It addresses… Read More
AI isn’t having an easy ride. The media and Wall Street swing wildly between extremes on any hint of a shift in AI sentiment. Dickens saw this coming: “It was the best of times, it was the worst of times, it was the age of wisdom, it was the age of foolishness, it was the epoch of belief, it was the epoch of incredulity, it was the season of … Read More
The 40-Year Evolution of Hardware-Assisted Verification — From In-Circuit Emulation to AI-Era Full-Stack Validation
For more than a decade, Hardware-Assisted Verification platforms have been the centerpiece of the verification toolbox. Today, no serious semiconductor program reaches tapeout without emulation or FPGA-prototyping… Read More
In the fast-evolving world of semiconductor design, creating a complex System-on-Chip (SoC) requires meticulous planning to ensure performance, power efficiency, and cost-effectiveness. Aion Silicon’s white paper, authored by Piyush Singh, outlines a streamlined methodology that leverages advanced modeling… Read More
By Andy Nightingale, VP of Product Management and Marketing
As AI adoption accelerates across markets, including automotive ADAS, large-scale compute, multimedia, and edge intelligence, the foundations of system-on-chip (SoC) designs are being pushed harder than ever. Modern AI engines generate tightly coordinated, … Read More
The explosive growth of AI and accelerated computing is placing unprecedented demands on system-on-chip (SoC) design. Modern AI workloads require extremely high bandwidth, ultra-low latency, and energy-efficient data movement across increasingly heterogeneous architectures. As SoCs scale to incorporate clusters of… Read More
IP-XACT, defined by IEEE 1685, is a standard that pulls together IP packaging, integration, and reuse. For anyone building modern SoCs (Systems on Chip), IP-XACT isn’t just another XML schema: it is a productivity multiplier and a risk-reduction tool that brings order to your electronic system design.
What is IP-XACT?
IP-XACT… Read More
In chiplet-based design we continue the march of Moore’s Law by scaling what we can put in a semiconductor package beyond the boundaries of what we can build on a single die. This style is already gaining traction in AI applications, high performance computing, and automotive, each of which aims to scale out to highly integrated … Read More
I am tracking the shift to multi-die design, so it’s good to see Arteris extend their NoC expertise, connecting chiplets across an interposer. After all, network connectivity needs don’t stop at the boundaries of chiplets. A multi-die package is at a logical level just a scaled-up SoC for which you still need traffic routing and… Read More
Modern semiconductor devices, a far cry from the chips we once knew, are now highly complex intelligent systems used in datacenters, communications infrastructure, in consumer electronics, automotive, home and office automation, almost everywhere. All such applications build around large subsystems, invariably compute,… Read More
