Future Semiconductor Technology Innovations

Future Semiconductor Technology Innovations
by Tom Dillinger on 07-19-2022 at 6:00 am

2D metals

At the recent VLSI Symposium on Technology and Circuits, Dr. Y.J. Mii, Senior Vice President of Research and Development at TSMC, gave a plenary talk entitled, “Semiconductor Innovations, from Device to System”.  The presentation offered insights into TSMC’s future R&D initiatives, beyond the current roadmap.  The associated… Read More


TSMC 2022 Technology Symposium Review – Process Technology Development

TSMC 2022 Technology Symposium Review – Process Technology Development
by Tom Dillinger on 06-22-2022 at 5:00 am

finFLEX

TSMC recently held their annual Technology Symposium in Santa Clara, CA.  The presentations provided a comprehensive overview of their status and upcoming roadmap, covering all facets of process technology and advanced packaging development.  This article will summarize the highlights of the process technology updates… Read More


IBM at IEDM

IBM at IEDM
by Scotten Jones on 01-10-2022 at 6:00 am

Vertical FET process

IBM transferred their semiconductor manufacturing to GLOBALFOUNDRIES several years ago but still maintains a multibillion-dollar research facility at Albany Nanotech. IBM is very active at conferences such as IEDM and appears to have a good public relations department because they get a lot of press.

At the Litho Workshop … Read More


TSMC Design Considerations for Gate-All-Around (GAA) Technology

TSMC Design Considerations for Gate-All-Around (GAA) Technology
by Tom Dillinger on 07-12-2021 at 6:00 am

mobility differences 3

The annual VLSI Symposium provides unique insights into R&D innovations in both circuits and technology.  Indeed, the papers presented are divided into two main tracks – Circuits and Technology.  In addition, the symposium offers workshops, forums, and short courses, providing a breadth of additional information.

At… Read More


Optimization for pFET Nanosheet Devices

Optimization for pFET Nanosheet Devices
by Tom Dillinger on 01-04-2021 at 6:00 am

Intel flow TEM

The next transition from current FinFET devices at advanced process nodes is the “nanosheet” device, as depicted in the figure below. [1]

The FinFET provides improved gate-to-channel electrostatic control compared to a planar device, where the gate traverses three sides of the fin.  The “gate-all-around” characteristics… Read More


IEDM 2019 – IBM and Leti

IEDM 2019 – IBM and Leti
by Scotten Jones on 01-08-2020 at 6:00 am

Slide3

IBM and Leti each presented several papers at IEDM including a joint nanosheet paper. I had the opportunity to sit down with Huiming Bu, director of advanced logic & memory tech and Veeraraghavan Basker, senior engineer from IBM and then in a separate interview Francois Andrieu, head of advanced CMOS laboratory and Shay Reboh,… Read More


IEDM 2017 – imec Charting the Future of Logic

IEDM 2017 – imec Charting the Future of Logic
by Scotten Jones on 01-04-2018 at 12:00 pm

At the IEDM 2017, imec held an imec technology forum and presented several papers, I also had the opportunity to interview Anda Mocuta director of technology solutions and enablement. In this article I will summarize the keys points of what I learned about the future of logic. I will follow this up with a later article covering memory.… Read More