Enabling the Ecosystem for True Heterogeneous 3D IC Designs

Enabling the Ecosystem for True Heterogeneous 3D IC Designs
by Kalar Rajendiran on 07-28-2025 at 10:00 am

The Shift to System Technology Co Optimization

The demand for higher performance, greater configurability, and more cost-effective solutions is pushing the industry toward heterogeneous integration and 3D integrated circuits (3D ICs). These solutions are no longer reserved for niche applications—they are rapidly becoming essential to mainstream semiconductor design.… Read More


Revolutionizing Simulation Turnaround: How Siemens’ SmartCompile Transforms SoC Verification

Revolutionizing Simulation Turnaround: How Siemens’ SmartCompile Transforms SoC Verification
by Kalar Rajendiran on 07-08-2025 at 10:00 am

SmartCompile

In the race to deliver ever-larger SoCs under shrinking schedules, simulation is becoming a bottleneck. With debug cycles constrained by long iteration times—even for minor code changes—teams are finding traditional flows too rigid and slow. The problem is further magnified in continuous integration and continuous deployment… Read More


Averting Hacks of PCIe® Transport using CMA/SPDM and Advanced Cryptographic Techniques

Averting Hacks of PCIe® Transport using CMA/SPDM and Advanced Cryptographic Techniques
by Kalar Rajendiran on 01-13-2025 at 10:00 am

CMA:SPDM Flow for Establishing a Secure Connection

In today’s digital landscape, data security has become an indispensable feature for any data transfer protocol, including Peripheral Component Interconnect Express (PCIe). With the rising frequency and sophistication of digital attacks, ensuring data integrity, confidentiality, and authenticity during PCIe transport… Read More


Reducing Electronic Systems Design Complexity with AI

Reducing Electronic Systems Design Complexity with AI
by Kalar Rajendiran on 07-20-2023 at 6:00 am

Siemens Reducing Complexity with AI Whitepaper Graphics

 

In the world of electronic systems design, complexity has always been a major challenge. As technology advances and demands for more efficient and powerful electronic devices grow, engineers face increasingly intricate design requirements. These complexities often lead to longer design cycles, increased costs, … Read More


Securing PCIe Transaction Layer Packet (TLP) Transfers Against Digital Attacks

Securing PCIe Transaction Layer Packet (TLP) Transfers Against Digital Attacks
by Kalar Rajendiran on 06-01-2023 at 10:00 am

PCIe TLP Encryption

In the fast moving world of data communications, the appetite for high speed data transfers is accompanied by a growing need for data confidentiality and integrity. The wildly popular PCIe interface standard for connectivity has not only been increasing data transfer rates but has also introduced an Integrity and Data Encryption… Read More


Emerging Stronger from the Downturn

Emerging Stronger from the Downturn
by Kalar Rajendiran on 05-16-2023 at 6:00 am

Full Flow from HL Synthesis through to GDSII Accelerates the creation of AI IP

It was refreshing to hear a talk focused on emerging stronger from the downturn when the news and media are focused on the gloom. At the recent Siemens EDA User2User conference, Joe Sawicki, executive vice president, IC, gave an uplifting keynote talk to the audience. He highlighted a secular growth trend happening in the semiconductor… Read More


Chiplet Modeling and Workflow Standardization Through CDX

Chiplet Modeling and Workflow Standardization Through CDX
by Kalar Rajendiran on 05-15-2023 at 6:00 am

Chiplet Integration Workflow

Chiplet is a hot topic in the semiconductor world these days. So much so that if one hasn’t heard that term, the person must be living on a very isolated islet. Humor aside, products built using chiplets-based methodology have been in existence for at least some years now. Companies such as Intel, AMD, Apple and others have integrated… Read More


Tessent SSN Enables Significant Test Time Savings for SoC ATPG

Tessent SSN Enables Significant Test Time Savings for SoC ATPG
by Kalar Rajendiran on 05-08-2023 at 6:00 am

Pattern Generation Block Level ATPG Flow

SoC test challenges arise due to the complexity and diversity of the functional blocks integrated into the chip. As SoCs become more complex, it becomes increasingly difficult to access all of the functional blocks within the chip for testing. SoCs also can contain billions of transistors, making it extremely time-consuming… Read More


Achieving Optimal PPA at Placement and Carrying it Through to Signoff

Achieving Optimal PPA at Placement and Carrying it Through to Signoff
by Kalar Rajendiran on 05-02-2023 at 10:00 am

PreRoute PostRoute Net Length Correlation

Performance, Power and Area (PPA) metrics are the driving force in the semiconductor market and impact all electronic products that are developed. PPA tradeoff decisions are not engineering decisions, but rather business decisions made by product companies as they decide to enter target end markets. As such, the sooner a company… Read More


The Increasing Gap between Semiconductor Companies and their Customers

The Increasing Gap between Semiconductor Companies and their Customers
by Rahul Razdan on 10-19-2022 at 6:00 am

figure1 4

Semiconductors sit at the heart of the electronics revolution, and the scaling enabled by Moore’s law has had a transformational impact on electronics as well as society.   Traditionally, the relationship between semiconductor companies and their customers has been a function of the volume driven by the customer.  In very … Read More