At the IEDM conference in December 2022, Imec presented “Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells,” I had a chance to not only read the paper and see it presented, but also to interview one of the authors Zsolt Tokie.
Logic designs are built up by standard cells such as inverters,… Read More
SEMICON West 2022 was held from July 12th to 14th at the Moscone Center in San Francisco.
On Monday the 11th before the show, Imec held a technology forum at the Marriott Marquee right around the corner from the Moscone center. In recent years the Imec forums have shifted away from the process technology I cover to more of a system and… Read More
At the VLSI Technology Symposium Imec presented on Buried Power Rails (BPR) and Backside Power Delivery (BSPD) in a paper entitled: “Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails”. I recently had a chance to interview one of the authors, Naoto Horiguchi about the work. I have interviewed … Read More
Today, the CMOS chip manufacturing is the pinnacle of the human technology defining economy, society and perhaps us as modern humans. This was highlighted by the recent chip shortage, followed by the ‘shocking’ realization that more than 80% of all chips are manufactured in the Far East.
Important decisions need to be taken by … Read More
IBM transferred their semiconductor manufacturing to GLOBALFOUNDRIES several years ago but still maintains a multibillion-dollar research facility at Albany Nanotech. IBM is very active at conferences such as IEDM and appears to have a good public relations department because they get a lot of press.
At the Litho Workshop … Read More
At the 2021 VLSI Technology Symposium, Imec presented on Ruthenium (Ru) and Molybdenum (Mo) as alternate Word Line (WL) materials for 3D NAND Flash “First Demonstration of Ruthenium and Molybdenum Word lines Integrated into 40nm Pitch 3D NAND Memory Devices”. I had an opportunity to interview one of the authors: Maarten Rosmeulen.… Read More
FinFETs devices are reaching their limits for scaling. Horizontal Nanosheets (HNS) are a type of Gate All Around (GAA) device that offers better scaling and performance per unit area. HNS is the logical next step from FinFETs because HNS processing is similar to FinFETs with a limited number of process changes required.
At the … Read More
At the 2021 Symposium on VLSI Technology and Circuits in June a short course was held on “Advanced Process and Devices Technology Toward 2nm-CMOS and Emerging Memory”. In this article I will review the first two presentations covering leading edge logic devices. The two presentations are complementary and provide and excellent… Read More
On Monday morning at IEDM, Sri Samavedam of Imec opened the technical program with a plenary talk entitled “Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips”. I am not generally a fan of plenary talks, I think the presenters often try to cover too much in their talks and end up not providing enough detail to be… Read More
The 2020 VLSI Technology Symposium was held as a virtual conference from June 14th through June 19th. At the symposium Imec gave an interesting paper on Monolithic CFET and I had a chance to interview one of the authors, Hiroaki Arimura.
It is well known in the industry that FinFETs (FF) are reaching the end of their scaling life. Samsung… Read More
