Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet

Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet
by Jonah McLeod on 09-09-2025 at 10:00 am

Rising Wafer

Can cash and IBM collaboration put Japan into premier-league chipmaking? Rapidus is betting billions it can.

When Japan announced the creation of Rapidus in 2022, the news was met with a mix of enthusiasm and skepticism. The company would enter the market at a time of escalating demand for semiconductor fabrication capacity to… Read More


Advancements in High-Density Front- and Backside Wafer Connectivity: Paving the Way for CMOS 2.0

Advancements in High-Density Front- and Backside Wafer Connectivity: Paving the Way for CMOS 2.0
by Admin on 08-30-2025 at 6:00 am

Example of a possible partitioning of a SoC in the CMOS 2.0 era

In the rapidly evolving semiconductor landscape, imec’s recent breakthroughs in wafer-to-wafer hybrid bonding and backside technologies are reshaping the future of compute systems. As detailed in their article, these innovations transition CMOS 2.0 from a conceptual framework to practical reality, enabling denser,… Read More


Podcast EP305: On Overview of imec’s XTCO Program with Dr. Julien Ryckaert

Podcast EP305: On Overview of imec’s XTCO Program with Dr. Julien Ryckaert
by Daniel Nenni on 08-29-2025 at 10:00 am

Dan is joined by Dr. Julien Ryckaert who joined imec as a mixed-signal designer in 2000, specializing in RF transceivers, ultra-low power circuit techniques, and analog-to-digital converters. In 2010, he joined imec’s process technology division in charge of design enablement for 3DIC technology. Since 2013, he oversees… Read More


IMEC’s Advanced Node Yield Model Now Addresses EUV Stochastics

IMEC’s Advanced Node Yield Model Now Addresses EUV Stochastics
by Fred Chen on 08-23-2025 at 8:00 am

EUV Stochastics

It lays the foundation for the Stochastics Resolution Gap

Chris Mack, the CTO of Fractilia, recently wrote of the “Stochastics Resolution Gap,” which is effectively limiting the manufacturability of EUV despite its ability to reach resolution limits approaching 10 nm in the lab [1,2]. As researchers have inevitably found, … Read More


XTCO: From Node Scaling to System Scaling

XTCO: From Node Scaling to System Scaling
by Admin on 08-10-2025 at 10:00 am

imec XTCO Image SemiWIki

imec XTCO (Cross-Technology Co-Optimization) is the natural successor to DTCO and STCO in an era where no single layer of the stack can deliver scaling alone. Instead of optimizing devices, interconnect, packaging, architecture, and software in isolation, XTCO treats them as one tightly coupled system with a shared budget … Read More


3D IC Design Ecosystem Panel at #61DAC

3D IC Design Ecosystem Panel at #61DAC
by Daniel Payne on 08-05-2024 at 10:00 am

bits per joule min

At #61DAC our very own Daniel Nenni from SemiWiki moderated an informative panel discussion on the topic of 3D IC Design Ecosystem. Panelists included: Deepak Kulkarni – AMD, Lalitha Immaneni – Intel Foundry, Trupti Deshpande – Qualcomm, Rob Aitken – CHIPS, Puneet Gupta – UCLA, Dragomir Milojevic – imec. Each panelist had a brief… Read More


SEMICON West- Jubilant huge crowds- HBM & AI everywhere – CHIPS Act & IMEC

SEMICON West- Jubilant huge crowds- HBM & AI everywhere – CHIPS Act & IMEC
by Robert Maire on 07-12-2024 at 6:00 am

Semicon West SF

– We just finished the most happy SEMICON West in a long time
– IMEC stole the show- HBM has more impact than size dictates
– Has Samsung lost its memory mojo? Is SK the new leader?
– AI brings new tech issues with it – TSMC is still industry King

Report from SEMICON West

The crowds at Semicon West were both… Read More


IEDM 2023 – Imec CFET

IEDM 2023 – Imec CFET
by Scotten Jones on 01-17-2024 at 6:00 am

29 1 Wed Horiguchi 3 final Page 04

At IEDM 2023, Naoto Horiguchi presented on CFETs and Middle of Line integration. I had a chance to speak with Naoto about this work and this write up is based on his presentation at IEDM and our follow up discussion. I always enjoy talking to Naoto, he is one of the leaders in logic technology development, explains the technology in … Read More


CEO Interview: Harry Peterson of Siloxit

CEO Interview: Harry Peterson of Siloxit
by Daniel Nenni on 08-04-2023 at 6:00 am

hwp photo

Harry Peterson is a mixed-signal chip designer with a BS in Physics from Caltech.  He managed IC design groups within Fairchild, Kodak, Philips, Northern Telecom, Toshiba and Pixelworks.  During sabbaticals he helped fly experiments on NASA’s orbiting satellite observatory (OSO-8) and build telescopes in the Canary… Read More


SPIE 2023 – imec Preparing for High-NA EUV

SPIE 2023 – imec Preparing for High-NA EUV
by Scotten Jones on 05-17-2023 at 6:00 am

Figure 1 Pellicle Transmission

The SPIE Advanced Lithography Conference was held in February. I recently had the opportunity to interview Steven Scheer, vice president of advanced patterning process and materials at imec and review selected papers that imec presented.

I asked Steve what the overarching message was at SPIE this year, he said readiness for … Read More