Generative AI for Silicon Design – Article 3 (Simulate My Design)

Generative AI for Silicon Design – Article 3 (Simulate My Design)
by Anshul Jain on 11-14-2023 at 10:00 am

Generative AI for Silicon Design

Generative AI has time and again showcased its power to understand, predict, and explain a myriad of phenomena. Beyond its famed applications in art and text, it’s making ripples in the niche realm of hardware engineering. In this article, our exploration focuses on the potential of Generative AI to comprehend and predict… Read More


Generative AI for Silicon Design – Article 2 (Debug My Waveform)

Generative AI for Silicon Design – Article 2 (Debug My Waveform)
by Anshul Jain on 11-01-2023 at 10:00 am

Generative AI for Silicon Design Article 2

Generative AI has been making waves across various industries, and its potential continues to expand. Among its many applications, one particularly intriguing area is the capacity of GenAI to explain digital design waveforms and act as a co-pilot for hardware engineers in the debugging process. In this article, we will explore

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Generative AI for Silicon Design – Article 1 (Code My FSM)

Generative AI for Silicon Design – Article 1 (Code My FSM)
by Anshul Jain on 10-24-2023 at 10:00 am

Generative AI for Silicon Design

In today’s fast-paced world, innovation in semiconductor design is a constant demand. The need for quicker, more accurate, and innovative solutions has paved the way for exploring the potential of Generative AI (#GenerativeAI) in the realm of semiconductor design development. Can it be done? Hell yeah! In this article… Read More


Long-standing Roadblock to Viable L4/L5 Autonomous Driving and Generative AI Inference at the Edge

Long-standing Roadblock to Viable L4/L5 Autonomous Driving and Generative AI Inference at the Edge
by Lauro Rizzatti on 10-11-2023 at 6:00 am

Table I

Two recent software-based algorithmic technologies –– autonomous driving (ADAS/AD) and generative AI (GenAI) –– are keeping the semiconductor engineering community up at night.

While ADAS at Level 2 and Level 3 are on track, AD at Levels 4 and 5 are far from reality, causing a drop in venture capital enthusiasm and money. Today,… Read More


Scaling LLMs with FPGA acceleration for generative AI

Scaling LLMs with FPGA acceleration for generative AI
by Don Dingee on 09-13-2023 at 6:00 am

Crucial to FPGA acceleration of generative AI is the 2D NoC in the Achronix Speedster 7t

Large language model (LLM) processing dominates many AI discussions today. The broad, rapid adoption of any application often brings an urgent need for scalability. GPU devotees are discovering that where one GPU may execute an LLM well, interconnecting many GPUs often doesn’t scale as hoped since latency starts piling up with… Read More


Synopsys Expands Synopsys.ai EDA Suite with Full-Stack Big Data Analytics Solution

Synopsys Expands Synopsys.ai EDA Suite with Full-Stack Big Data Analytics Solution
by Kalar Rajendiran on 09-11-2023 at 10:00 am

Wafer Circuit Detail

More than two years ago, Synopsys launched its AI-driven design space optimization (DSO.ai) capability. It is part of the company’s Synopsys.ai EDA suite, an outcome of its overarching AI initiative. Since then, DSO.ai has boosted designer productivity and has been leveraged for 270 production tape-outs. DSO.ai uses machine… Read More


Breakthrough Gains in RTL Productivity and Quality of Results with Cadence Joules RTL Design Studio

Breakthrough Gains in RTL Productivity and Quality of Results with Cadence Joules RTL Design Studio
by Kalar Rajendiran on 08-08-2023 at 10:00 am

Joules RTL Design Studio Benefits

Register Transfer Level (RTL) is a crucial and valuable concept in digital hardware design. Over the years, it has played a fundamental role in enabling design of complex digital chips. By abstracting away implementation details and providing a clear description of digital behavior, RTL has contributed significantly to the… Read More


A Bold View of Future Product Development with Matt Genovese

A Bold View of Future Product Development with Matt Genovese
by Mike Gianfagna on 08-01-2023 at 10:00 am

Matt Genovese

Matt Genovese is the founder of Planorama Design, a software requirements and user experience design professional services company.  The company designs simple and intuitive software and IoT product user interfaces for complex, technical applications and systems.  Its unique and proven approach reduces client development… Read More


The Efabless Generative AI Challenges and Why They Matter

The Efabless Generative AI Challenges and Why They Matter
by Daniel Nenni on 07-20-2023 at 10:00 am

Efabless Banner for SemiWiki

Last week, Efabless announced the second edition of its AI Generated Open-Source Silicon Design Challenge series.  As we discussed in earlier blogs, the first challenge was a great success with twelve submissions and six successful designs created in just three weeks. The contestants used natural language prompts to create… Read More


Why Generative AI for Chip Design is a Game Changer

Why Generative AI for Chip Design is a Game Changer
by Daniel Nenni on 05-22-2023 at 10:00 am

Efabless AI Generated Design Challenge SemiWiki 1

AI-generated chip design is progressing at an incredible pace!

Earlier this week, I wrote about the Efabless AI Generated Open–Source Silicon Design Challenge.  If you haven’t done so already, take a closer look at the challenge and see first-hand what this is all about.  In talking to Mike Wishart and Mohamed Kassem, co-founders… Read More