The VLSI Symposium on Technology and Circuits provides a deep dive on recent technical advances, as well as a view into the research efforts that will be transitioning to production in the near future. In a short course presentation at the Symposium, Marko Radosavljevic, from the Components Research group at Intel, provided … Read More
Highlights of the “Intel Accelerated” Roadmap Presentation
Intel recently provided a detailed silicon process and advanced packaging technology roadmap presentation, entitled “Intel Accelerated”. The roadmap timeline extended out to 2024, with discussions of Intel client, data center, and GPU product releases, and especially, the underlying technologies to be … Read More
TSMC Design Considerations for Gate-All-Around (GAA) Technology
The annual VLSI Symposium provides unique insights into R&D innovations in both circuits and technology. Indeed, the papers presented are divided into two main tracks – Circuits and Technology. In addition, the symposium offers workshops, forums, and short courses, providing a breadth of additional information.
At… Read More
Optimization for pFET Nanosheet Devices
The next transition from current FinFET devices at advanced process nodes is the “nanosheet” device, as depicted in the figure below. 
The FinFET provides improved gate-to-channel electrostatic control compared to a planar device, where the gate traverses three sides of the fin. The “gate-all-around” characteristics… Read More
MOSFET Gate Length Scaling Limit at Reduced Threshold Voltages
As transistor dimensions shrink to follow Moore’s Law, the functionality of the gate used to switch on or off the current is actually being degraded by the short channel effect (SCE) [1-5]. Moreover, the simultaneous reduction of voltage aggravates the degradation, as will be discussed below.
A Practical Lower Limit of… Read More