GSA Memory+ Conference in Taiwan

GSA Memory+ Conference in Taiwan
by Paul McLellan on 10-18-2013 at 3:02 pm

The GSA Memory+ conference Taiwan will take place on (Halloween!) October 31, 2013 at the Regent Taipei, Taiwan. The main theme of this year is highlighting Memory—the Critical Enabler for Prominent and Emerging Applications in System Logic Solutions.

GSA Memory+ Conference is the global industry event dedicated to all memory… Read More


Using OTP Memories To Keep SoC Power Down

Using OTP Memories To Keep SoC Power Down
by Paul McLellan on 09-20-2013 at 1:43 pm

Virtually all SoCs require one-time programmable (OTP) memory. Each SoC is different, of course, but two main uses are large memories for holding boot and programming code and small memories for holding encryption keys and trimming parameters, such as radio tuning information and so on.

There are alternatives to putting an OTP… Read More


A Brief History of TSMC’s OIP part 2

A Brief History of TSMC’s OIP part 2
by Paul McLellan on 09-18-2013 at 11:00 pm

The existence of TSMC’s Open Innovation Platform (OIP) program further sped up disaggregation of the semiconductor supply chain. Partly, this was enabled by the existence of a healthy EDA industry and an increasingly healthy IP industry. As chip designs had grown more complex and entered the system-on-chip (SoC) era, the amount… Read More


Are 28nm Transistors the Cheapest…Forever?

Are 28nm Transistors the Cheapest…Forever?
by Paul McLellan on 09-17-2013 at 10:43 am

It is beginning to look as if 28nm transistors, which are the cheapest per million gates compared to any earlier process such as 45nm, may also be the cheapest per million gates compared to any later process such as 20nm.

What we know so far: FinFET seems to be difficult technology because of the 3D structure and so the novel manufacturing… Read More


TSMC’s 16FinFET and 3D IC Reference Flows

TSMC’s 16FinFET and 3D IC Reference Flows
by Paul McLellan on 09-17-2013 at 2:01 am

Today TSMC announced three reference flows that they have been working on along with various EDA vendors (and ARM and perhaps other IP suppliers). The three new flows are:

  • 16FinFET Digital Reference Flow. Obviously this has full support for non-planar FinFET transistors including extraction, quantized pitch placement, low-vdd
Read More

Semiconductor Manufacturing in India?

Semiconductor Manufacturing in India?
by Pawan Fangaria on 09-15-2013 at 11:30 am


Last week I heard about the Indian Cabinet approving the proposal for setting up of two Fabs in India. One led by IBM, Tower Jazzand JP Associates(an Indian business house), and the other led by HSMC(Hindustan Semiconductor Manufacturing Co.), ST Microelectronicsand Silterra. Indian Semiconductor community including IESARead More


Sidense and TSMC Processes

Sidense and TSMC Processes
by Paul McLellan on 09-14-2013 at 2:21 pm

I’ve written before about the basic capabilities of Sidense’s single transistor one-time programmable memory products (1T-OTP). Just to summarize, it is an anti-fuse device that works by permanently rupturing the gate oxide under the bit-cells storage transistor, something that is obviously irreversible.… Read More


Intel Quark: Synthesizable Core?

Intel Quark: Synthesizable Core?
by Paul McLellan on 09-10-2013 at 1:43 pm

At IDF Brian Krzanich gave the keynote. I won’t summarize the whole thing here but just talk about one part that was something they had actually managed to keep secret ahead of time: Quark.

Quark is a synthesizable core. It uses 1/10th power of Atom and is 1/5 size. Now I am writing this, I don’t know if this is a fair comparison… Read More


GlobalFoundries Expands in Singapore

GlobalFoundries Expands in Singapore
by Paul McLellan on 09-09-2013 at 8:30 pm

GlobalFoundries has been in Singapore for a long time. Longer than GlobalFoundries has existed in fact. Chartered Semiconductor was started in Singapore in 1987 and GF acquired them in early 2010 less than a year after they were created by spinning out the manufacturing arm of AMD. When GF was started their state of the art fab was… Read More


TSMC OIP: Mentor’s 5 Presentations

TSMC OIP: Mentor’s 5 Presentations
by Paul McLellan on 09-09-2013 at 6:30 pm

At TSMC’s OIP on October 1st, Mentor Graphics have 5 different presentations. Collect the whole set!

11am, EDA track. Design Reliability with Calibre Smartfill and PERC. Muni Mohan of Broadcom and Jeff Wilson of Mentor. New methodologies were invented for 28nm for smart fill meeting DFM requirements (and at 20nm me may … Read More