Vlang – Opportunities Galore for Productivity & Performance

Vlang – Opportunities Galore for Productivity & Performance
by Pawan Fangaria on 08-19-2014 at 2:01 pm

Yes, verification technologies are open to innovation for improved productivity and performance in the face of ever growing SoC/IP design sizes and complexities. There is not much scope left in processor speed to improve, other than multi-core processors in servers which again need software properly architected to be thread-able… Read More


Accelerating SoC Verification Through HLS

Accelerating SoC Verification Through HLS
by Pawan Fangaria on 07-28-2014 at 3:00 pm

Once upon a time there was a struggle for verification completion of semiconductor designs at gate level. Today, beyond imagination, there is a struggle to verify a design with billions of gates at the RTL level which may never complete. The designs are large SoCs with complex architectures and several constraints of area, performance,… Read More


Two New ESL Tools for Power and Thermal at DAC

Two New ESL Tools for Power and Thermal at DAC
by Daniel Payne on 05-27-2014 at 6:47 pm

Image RemovedGary Smith published a list of what to see at DAC, and I noticed that he listed DOCEA Power in a category of ESL Thermal. I’ll be meeting the DOCEA engineers on Wednesday at DAC to learn more about their two newest ESL products:

  • Thermal Profiler
  • Power Intelligence

In general DOCEA Power tools allow you to manage … Read More


Different Approaches to System Level Power Modeling and Analysis for Early Design Phases

Different Approaches to System Level Power Modeling and Analysis for Early Design Phases
by Daniel Payne on 05-27-2014 at 3:14 pm

At DATEthis year in Dresden, Bernhard Fischer from Siemens CT(Corporate Technology) has presented an interesting summary of the various techniques used for power modeling and analysis at the architectural level. He went through the pros and cons of using spreadsheets, timed virtual platforms annotated with power numbers … Read More


Power and Thermal Simulation in ESL Verification Flows

Power and Thermal Simulation in ESL Verification Flows
by Daniel Payne on 04-18-2014 at 8:11 pm

At the recent DVcon there was a keen focus on design verification and validation. Much of the attention is on Logic/circuit design verification, UVM, and IP verification. At the system level functional verification has improved to comprehend complex hardware and software interaction using Virtual Platforms/SystemC and Transaction… Read More


TLM Modeling Environment Goes Commercial

TLM Modeling Environment Goes Commercial
by Daniel Payne on 03-20-2014 at 6:00 pm

The most successful EDA companies typically choose a domain where they have deep knowledge, then serve a few leading-edge customers that are willing to work with a start-up in exchange for early access to that new technology. The theory is that if you can satisfy the leading-edge customer then you can also satisfy the rest of the … Read More


Key Ingredients for ESL Power Modeling, Simulation, Analysis and Optimzations

Key Ingredients for ESL Power Modeling, Simulation, Analysis and Optimzations
by Daniel Payne on 03-07-2014 at 6:00 pm

There’s a French EDA company named DOCEA Powerthat is uniquely focused on power analysis at the ESL level and I had a chance to interview Ridha Hamza to get new insight on ESL design challenges and their approach. Ridha started out doing SRAM design at STMicroelectornics in the 1990’s, moved into the emerging field … Read More


Carbon Design Systems – Secret of Success

Carbon Design Systems – Secret of Success
by Pawan Fangaria on 02-19-2014 at 11:00 am

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Last week, after learning from the press releaseof Carbonabout its rocking sustained growth with record-breaking revenue and a thumping 46% increase in bookings, I was interested to know some more details about what drives Carbon to such an amazing performance in an EDA market that is generally prone to growth of… Read More


How to Design an LTE Modem

How to Design an LTE Modem
by Paul McLellan on 09-16-2013 at 4:24 pm

Image RemovedDesigning an LTE modem is an interesting case study in architectural and system level design because it is pretty much on the limit of what is possible in a current process node such as 28nm. I talked to Johannes Stahl of Synopsys about how you would accomplish this with the Synopsys suite of system level tools. He is the… Read More