Who needs DDR4 PHY running at 2667 Mbps?

Who needs DDR4 PHY running at 2667 Mbps?
by Eric Esteve on 02-02-2014 at 11:15 am

As of today, DDR4 are targeting server, networking and consumer applications, and it will take another year before we use DDR4 equipped PC at home. In fact, a majority of consumers will rather buy a smartphone or tablet than a PC, most of these devices coming with PLDDR2 and only a few high-end tablets are equipped with LPDDR3 memory.… Read More


Remember FPGA Memory

Remember FPGA Memory
by Luke Miller on 06-25-2013 at 3:10 pm

We must admit the excitement of the FinFETs and all that coupled with the enormous amount of DSPs and BRAMs in the FPGA world is very cool. They even have ARMs, and I highly recommend that they get Legs then they can run around and everything and fit in with the rest of us. Perhaps the Feds can grant them immigration status and they could… Read More


Cadence September News: strong IP and VIP focus

Cadence September News: strong IP and VIP focus
by Eric Esteve on 09-14-2012 at 4:25 am

There are three articles on the front page, in the September release of Cadence newsletter, all of them are dedicated to either IP (DDR4), VIP (NVM express VIP being used at Samsung) or Martin Lund. You can read Martin’s interview here and/or take a look at what I write about him this summer. This strong focus on IP, and in fact on Interface… Read More


Is DDR4 a bridge too far?

Is DDR4 a bridge too far?
by Don Dingee on 09-11-2012 at 8:30 pm

We’ve gone through two decades where the PC market made the rules for technology. The industry faces a question now: Can a new technology go mainstream without the PC?

By now, you’ve certainly read the news from Cadence on their DDR4 IP for TSMC 28nm. They are claiming a PHY implementation that exceeds the data rates specified for … Read More


Memory Controller IP, battle field where Cadence and Synopsys are really fighting face to face. Today let’s have a look at Cadence’s strategy.

Memory Controller IP, battle field where Cadence and Synopsys are really fighting face to face. Today let’s have a look at Cadence’s strategy.
by Eric Esteve on 01-12-2012 at 9:45 am

I have shared with you last year some strategic information released by Cadence in April about their IP strategy, more specifically about the launch of the DDR4 Controller IP. And try to understand Cadence strategy about Interface IP in general (USB, PCIe, SATA, DDRn, HDMI, MIPI…) and how Cadence is positioned in respect with their… Read More


Interface Protocols, USB3, HDMI, MIPI… the winner and losers in 2011

Interface Protocols, USB3, HDMI, MIPI… the winner and losers in 2011
by Eric Esteve on 01-07-2012 at 11:30 am

Releasing a new protocol like ThunderBolt, HDMI or SuperSpeed USB has not only to do with bandwidth performance or form factor of the connector as a guarantee of success. Some non-scientific parameters also play a role in the alchemy, that’s why forecasting the success of a certain protocol is such a hard task, and can’t be reduced… Read More


Synopsys Awarded TSMC’s Interface IP Partner of the Year

Synopsys Awarded TSMC’s Interface IP Partner of the Year
by Eric Esteve on 11-09-2011 at 9:19 am

Is it surprising to see that Synopsys has been selected Interface IP partner of the year by TSMC? Not really, as the company is the clear leader on this IP market segment (which includes USB, PCI Express, SATA, DDRn, HDMI, MIPI and others protocols like Ethernet, DisplayPort, Hyper Transport, Infiniband, Serial RapidIO…). But,… Read More


Cadence Verification IP Technical Seminar!

Cadence Verification IP Technical Seminar!
by Daniel Nenni on 08-22-2011 at 11:43 am

According to trusted sources it costs upwards of $50M to design a 40nm SoC down to the GDS. Semiconductor IP is a fast growing part of that equation and functional verification of that IP is critical. Hardware complexity growth continues to follow Moore’s Law but verification complexity is even more challenging. In fact, IP verification… Read More


Cadence VIP Seminar: next stop after Denali party, August 25th in San Jose

Cadence VIP Seminar: next stop after Denali party, August 25th in San Jose
by Eric Esteve on 08-15-2011 at 10:42 am

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If you did not have the chance to attend the famous Denali party at DAC 2011, you may want to go to Cadence VIP seminar to be held on Thursday, August 25, 2011, from 1:00 – 4:15pm at Cadence Headquarters: 2655 Seely Avenue, San Jose, Building 10. To register, click here. The atmosphere could be slightly different, as during DenaliRead More


DDR4 Controller IP, Cadence IP strategy… and Synopsys

DDR4 Controller IP, Cadence IP strategy… and Synopsys
by Eric Esteve on 04-14-2011 at 4:17 am


I will share with you some strategic information released by Cadence last week about their IP strategy, more specifically about the launch of the DDR4 Controller IP. And try to understand Cadence strategy about Interface IP in general (USB, PCIe, SATA, DDRn, HDMI, MIPI…) and how Cadence is positioned in respect with their closestRead More