Which High B/W Memory to Select after DDR4?

Which High B/W Memory to Select after DDR4?
by Eric Esteve on 07-11-2015 at 6:00 am

Once upon a time, RAM technology was the driver of the semiconductor process. DRAM products were the first to be designed on a newest technology node and DRAM was used as a process driver. It was 30 years ago and the most aggressive process nodes were ranging between 1um and 1.5 um (1 500 nm!). Then in the 1990 the Synchronous Dynamic … Read More


Synopsy Eats Their Own Dogfood

Synopsy Eats Their Own Dogfood
by Paul McLellan on 06-29-2015 at 7:00 am

One of the most interesting presentations that I went to was the last presentation at the Synopsys Custom Lunch (no, the lunch wasn’t custom, we all got the same, but the presentations were about custom design). Since the last presentation was by Synopsys themselves and not by a customer, it wouldn’t seem promising that it could … Read More


Sonics’ New NoC

Sonics’ New NoC
by Paul McLellan on 06-23-2015 at 7:00 am

Today Sonics announced the latest version of their network-on-chip (NoC) technology, SonicsGN-3.0. As with any new release there are lots of improvements that are of interest mainly to existing users, but the big area with increased capability is the expanded interleaved memory technology (IMT). This was first introduced … Read More


IP-SoC 2014 Top Class Presentations…

IP-SoC 2014 Top Class Presentations…
by Eric Esteve on 11-12-2014 at 1:00 pm

… were given to an ever shrinking audience. This is IP-SoC paradox: audience has enjoyed very good presentations made by Cadence, Synopsys or ST-Microelectronic, to name just a few. As far as I am concerned, I was happy to present the “Interface IP Winners and Losers (Protocols)” in the amphitheater during the first day, enjoying… Read More


Interface IP Protocols: Status

Interface IP Protocols: Status
by Eric Esteve on 09-16-2014 at 3:52 am

If your company develops Design IP to support well-known protocols like USB, PCIe, HDMI, DDRn memory controller, MIPI specification (and more), it’s crucial to know your competition, the market size by segment, and even more important the market potential by segment. The latest can be obtained by the Compound Annual Growth Rate… Read More


Cadence white paper helps you selecting what come after DDR4

Cadence white paper helps you selecting what come after DDR4
by Eric Esteve on 08-23-2014 at 4:49 am

The DRAM market is shaking… In 2014, analysts predict that LPDDR4 will surpass DDR4 for the first time. When releasing DDR4 standard, JEDEC has clearly stated that the industry should not expect any DDR5. Does this means that DRAM technology new development is ending with DDR4? According with Mike Howard, principal analyst at … Read More


Synopsys Galaxy Platform & Lynx Design System supports FD-SOI

Synopsys Galaxy Platform & Lynx Design System supports FD-SOI
by Eric Esteve on 06-05-2014 at 11:36 am

This is a new brick that Synopsys brings to build FD-SOI credibility. We have talked at Semiwiki about FD-SOI technology developed by the LETI and STM, and recently endorsed by Samsung Foundry, offering a more than credible second source to STM. And we have said that the FD-SOI introduction will need to be supported by EDA and IP vendors… Read More


Cadence Go (war-game) strategy

Cadence Go (war-game) strategy
by Eric Esteve on 05-26-2014 at 8:19 am

I was attending to CDN-Live in Munich last week, so I was expecting Cadence to announce new IP related acquisition like Lip-Bu Tan did last year (Cosmic Circuit, Evatronix and Tensilica). In fact, Lip-Bu was not in Munich and Charlie Huang, SVP Worldwide Field Operations and System & Verification Group, was holding the morning… Read More


A Brief History of Mobiveil

A Brief History of Mobiveil
by Daniel Nenni on 04-03-2014 at 8:00 am

Semiconductor IP is a relatively established frontier for innovation in Silicon Valley but it is not as easy as it looks. It certainly is not as easy as the two year old start-up Mobiveil has made it look. With a team of more than 100, led by experienced Semiconductor IP professionals, Mobiveil already has a portfolio of silicon proven… Read More


Automating PCB Timing Closure, Saving Up to 67%

Automating PCB Timing Closure, Saving Up to 67%
by Daniel Payne on 03-05-2014 at 10:10 am

The benefits of using EDA software is that it can automate a manual process, like PCB timing closure, saving you both time and engineering effort. This point was demonstrated today as Cadenceadded new timing-closure automation to their Allegroproduct family, calling it Allegro TimingVision. On Tuesday I spoke with Hemant ShahRead More