Semiconductor Security and Sleep Loss

Semiconductor Security and Sleep Loss
by Daniel Nenni on 02-11-2019 at 12:00 pm

One of the semiconductor topics that keeps me up at night is security. We track security related topics on SemiWiki and while the results are encouraging, we still have a very long way to go. Over the last three years we have published 148 security related blogs that have garnered a little more than 400,000 views. Security touches … Read More


TSMC and Semiconductors 2019 and Beyond

TSMC and Semiconductors 2019 and Beyond
by Daniel Nenni on 01-22-2019 at 7:00 am

TSMC has always been my bellwether and for 2019 I think we need to pay careful attention. Bad economic news has been spreading inside the fabless semiconductor ecosystem (tool and IP budgets have been tightening) but I think it is a bit premature. Let’s take a look at the TSMC 2018 Q4 earnings call and talk more about it in the comments… Read More


CNBC Qualcomm and SemiWiki

CNBC Qualcomm and SemiWiki
by Daniel Nenni on 01-18-2019 at 7:00 am

Over the holidays I did an interview with CNBC on the subject of Qualcomm. The producer had read the History of Qualcomm chapter in our book Mobile Unleashed and wanted to base a 15 minute report on it. The interview lasted 90 minutes but of course only snippets of what I said were used. You can see the recorded report by clicking on the… Read More


IEDM 2018 Trip Report!

IEDM 2018 Trip Report!
by Daniel Nenni on 12-10-2018 at 7:00 am

Hello, my name is Daniel Nenni and I am a semiconductor conference addict. I just can’t seem to get enough. The semiconductor ecosystem is very wide now and moves so quickly it is nearly impossible to keep up without constant conference attendance. As a SemiWiki contributor not only do I get free conference passes, I get access to … Read More


Improving Library Characterization with Machine Learning!

Improving Library Characterization with Machine Learning!
by Daniel Nenni on 12-04-2018 at 7:00 am

For SOC designers that are waiting for library models the saying “give me liberty or give me death” is especially apropos. Without libraries to support the timing flow, SOC design progress can grind to a halt. As is often the case, more than just a few PVT corners are needed. Years ago, corners were what the term sounded like – the 4 corners… Read More


Eliminate PCB Re Spins using an Integrated Multi Dimensional Verification Platform

Eliminate PCB Re Spins using an Integrated Multi Dimensional Verification Platform
by Daniel Nenni on 11-15-2018 at 12:00 pm

The rapidly increasing complexity of today’s designs, combined with schedule pressure to deliver innovative products to market as quickly as possible, strains engineering resources to the limit, often to the point of breaking. As a result, 17% of all projects get canceled, and another 28% miss their target release date (Source:… Read More


Intel Diversity Semiconductors

Intel Diversity Semiconductors
by Daniel Nenni on 11-12-2018 at 7:00 am

Growing up in a military family, mostly in California, I would consider my cultural diversity life experience to be more than most. I remember in the 1960s some older folks were chattering about a colored family moving into our neighborhood and they had a son my age. Imagine my excitement as a child in having a multicolored friend!… Read More


Honey I Shrunk the EDA TAM

Honey I Shrunk the EDA TAM
by Daniel Nenni on 10-19-2018 at 7:00 am

The “20 Questions with Wally Rhines” series continues

Throughout the history of the EDA industry, pricing models have caused discontinuities in the way the industry operates. For a variety of competitive reasons, individual companies have developed ways to change the pricing model in an attempt to secure competitive… Read More


Crossfire Baseline Checks for Clean IP at TSMC OIP

Crossfire Baseline Checks for Clean IP at TSMC OIP
by Daniel Nenni on 09-26-2018 at 12:00 pm

IP must be properly qualified before attempting to use them in any IC design flow. One cannot wait to catch issues further down the chip design cycle. Waiting for issues to appear during design verification poses extremely high risks, including schedule slippage. For example, connection errors in transistor bulk terminals where… Read More


Turnkey 2.5D HBM2 Custom SoC SiP Solution for Deep Learning and Networking Applications

Turnkey 2.5D HBM2 Custom SoC SiP Solution for Deep Learning and Networking Applications
by Daniel Nenni on 09-07-2018 at 7:00 am

Before we jump into the specifics, let us understand what’s driving custom solutions in the high performance computing and networking space. It’s the growing demand for core capacity and greater performance, which is due to the increase in the level of parallelism and multitasking required to handle the enormous amount of data… Read More