Up front phases improve CDC analysis

Up front phases improve CDC analysis
by Don Dingee on 09-19-2016 at 4:00 pm

Many tools find clock domain crossings (CDCs) in FPGA designs. Some don’t find the right ones since they don’t comprehend things like in-house synchronizer constructs. Some find too many based on misunderstanding intent, inaccurate constraints, and other factors that lead to noise.… Read More


Dominating FPGA clock domains and CDCs

Dominating FPGA clock domains and CDCs
by Don Dingee on 09-26-2014 at 7:00 am

Multiple clock domains in FPGAs have simplified some aspects of designs, allowing effective partitioning of logic. As FPGA architectures get more flexible in how clock domains, regions, or networks are available, the probability of signals crossing clock domains has gone way up.… Read More


An Approach to Clock Domain Crossing for SoC Designs

An Approach to Clock Domain Crossing for SoC Designs
by Daniel Payne on 07-06-2014 at 12:20 am

Blogger Pawan Fangaria wrote about Clock Domain Crossing(CDC) a few weeks ago, and so I followed up tonight and watched a webinarabout CDC presented by Ravindra Anejaof Atrenta. An RTL design engineer would ultimately want a CDC verification tool that offers:

  • Fast throughput and thoroughness
  • Ability to debug and fix the source
Read More

Hierarchical Clock Domain Crossing

Hierarchical Clock Domain Crossing
by Paul McLellan on 10-23-2013 at 1:31 pm

One of the first blogs I wrote on SemiWiki was on clock domain crossing (CDC). I thought it was rather a specialized subject, a sort of minority interest. It turned out to be one of the most-read blogs I’ve written. Modern SoCs have lots of unrelated clocks, maybe hundreds, and so ensuring that signals going from one clock domain… Read More


The never-ending quest to kill metastability

The never-ending quest to kill metastability
by Don Dingee on 05-28-2013 at 4:00 pm

The difficulty of an engineering problem can be gauged by two things:
1) The number of attempts to generate a solution.
2) The degree of hyperbole used to describe the effectiveness of the latest solution.

The problem many folks in the EDA industry are after right now is clock domain crossings (CDCs) and the resulting metastability… Read More


Clock Domain Crossing, a potted history

Clock Domain Crossing, a potted history
by Paul McLellan on 03-03-2011 at 11:23 am

Yesterday I talked to Shaker Sarwary, the senior product director for Atrenta’s clock-domain crossing (CDC) product SpyGlass-CDC. I asked him how it came about. The product was originally started nearly 8 years ago, around the time Atrenta itself got going. Shaker got involved about 5 years ago.

Image RemovedOriginally… Read More


Clock Domain Crossing (CDC) Verification

Clock Domain Crossing (CDC) Verification
by Paul McLellan on 02-21-2011 at 6:12 pm

Multiple, independent clocks are quintessential in SoCs and other complex ASICs today. In some cases, such as in large communications processors, clock domains may number in the hundreds. Clock domain crossings pose a growing challenge to chip designers, and constitute a major source of design errors–errors that canRead More