Tag: chiplet

Webinar: Simplifying Interface Protocol Verification with Veloce Transactor Library

Webinar: Simplifying Interface Protocol Verification with Veloce Transactor Library
by Admin on 04-09-2025 at 2:36 am

As hyperscaler chiplet and SoCs grow in complexity, integrating and validating multiple high-speed and low-speed interface protocols—such as PCIe, CXL, UCIe, AMBA, AXI, AHB, CHI, CSI2, and DSI2, can be a significant challenge. Design Verification Engineers and Technical Managers must ensure seamless protocol compliance

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Webinar: Synopsys Collaboration Framework to Boost SoC/Chiplet Architecture Performance Analysis and Optimization

Webinar: Synopsys Collaboration Framework to Boost SoC/Chiplet Architecture Performance Analysis and Optimization
by Admin on 02-20-2025 at 6:46 pm

Date: March, 13 – 9 a.m. PST

Using virtual prototypes alongside early accessible performance models of new SoC or Chiplet architectures has become the de facto standard for early architecture performance modeling, exploration, and analysis. However, as designs and tools become increasingly complex, these virtual

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Outlook 2025 with David Hwang of Alchip

Outlook 2025 with David Hwang of Alchip
by Daniel Nenni on 02-17-2025 at 10:00 am
Categories: 3D IC, AI, Alchip, Chiplet, Semiconductor Services

Dave Huang

Dave Hwang joined Alchip in 2021 as General Manager of Alchip’s North America Business Unit.  He also serves as Senior Vice President, Business Development.  Prior to join Alchip, Dave served as Vice President, Worldwide Sales and Marketing for Global Unichip and in a variety of management and technical roles at TSMC.  He holds… Read More

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2025 Outlook Anna Fontanelli MZ Technologies

2025 Outlook Anna Fontanelli MZ Technologies
by Daniel Nenni on 02-12-2025 at 10:00 am
Categories: 3D IC, Chiplet, EDA, MZ Technologies

ANNA

Anna Fontanelli, CEO of MZ Technologies, is a silicon executive with more than 35 years of expertise in managing complex R&D organizations/programs to give birth to innovative EDA technologies. Strong communication skills and proven ability to lead distributed, cross functional teams in international environments.… Read More

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Embracing the Chiplet Journey: The Shift to Chiplet-Based Architectures

Embracing the Chiplet Journey: The Shift to Chiplet-Based Architectures
by Kalar Rajendiran on 02-12-2025 at 6:00 am
Categories: 3D IC, Automotive, Cadence, Chiplet, EDA, IP

Chiplets A New Abstraction Layer

The semiconductor industry is facing a paradigm shift. Traditional scaling, once driven by Moore’s Law, is slowing down. For years, moving to smaller process nodes led to lower transistor costs and better performance. However, scaling from node to node now offers fewer benefits as wafer costs rise much more than the historical… Read More

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Chiplets-Based Systems: Keysight’s Role in Design, Testing, and Data Management

Chiplets-Based Systems: Keysight’s Role in Design, Testing, and Data Management
by Kalar Rajendiran on 02-11-2025 at 6:00 am
Categories: 3D IC, Chiplet, EDA, Keysight EDA

Voltage Transfer Function Crrosstalk Limit

Keysight, with deep roots tracing back to Hewlett-Packard, has long been at the forefront of innovation in electronic design and testing. It manufactures electronics test and measurement equipment and software. The company also owns its own foundry and makes custom chips and packages for its instrumentation business. Many… Read More

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Will 50% of New High Performance Computing (HPC) Chip Designs be Multi-Die in 2025?

Will 50% of New High Performance Computing (HPC) Chip Designs be Multi-Die in 2025?
by Kalar Rajendiran on 01-28-2025 at 6:00 am
Categories: 3D IC, Chiplet, EDA, IP, Synopsys
2 Comments

Synopsys Predictions for Multi Die Designs in 2025

Predictions in technology adoption often hinge on a delicate balance between technical feasibility and market dynamics. While business considerations play a pivotal role, the technical category reasons for the success or failure of a prediction are more tangible and often easier to identify—if scrutinized with care. However,… Read More

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Heterogeneous 2D/3D Packaging Challenges

Heterogeneous 2D/3D Packaging Challenges
by Daniel Payne on 01-27-2025 at 10:00 am
Categories: 3D IC, EDA, Siemens EDA

Innovator3D IC flow min

A growing trend in system design is the use of multiple ICs mounted in advanced packages, especially in high-performance computing and AI. These modern packages now integrate multiple ICs, often with high-bandwidth memory (HBM), resulting in hundreds of thousands of connections that need proper verification. Traditional… Read More

Webinar: The Impact on the Automotive Market as Chips Transform Into 3D Systems

Webinar: The Impact on the Automotive Market as Chips Transform Into 3D Systems
by Admin on 01-24-2025 at 1:27 pm

The automotive industry stands on the cusp of a technological renaissance, ushering in an era where vehicles aren’t just tools of transportation, but interconnected nodes within a vast network of software-defined mobility. Central to this transformation is the concept of chiplets—miniaturized, modular components… Read More

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Defect-Pattern Leveraged Inherent Fingerprinting of Advanced IC Package with TRI

Defect-Pattern Leveraged Inherent Fingerprinting of Advanced IC Package with TRI
by Navid Asadizanjani on 10-29-2024 at 10:00 am
Categories: Chiplet, Security

Article 1 figure 1 (1)

In the quest to secure the authenticity and ownership of advanced integrated circuit (IC) packages, a novel approach has been introduced in this paper that capitalizes on the inherent physical discrepancies within these components. This method, distinct from traditional strategies like physical unclonable functions (PUFs)… Read More