Does Processor IP still get the Lion’s share in 2013?

Does Processor IP still get the Lion’s share in 2013?
by Eric Esteve on 04-17-2014 at 1:00 pm

I think that the answer is pretty obvious, but the interesting point is to figure out which processor type, and which part of revenues, up-front license or royalties? One of my customers, let’s call him Mr. X, ask me to clarify this point. Mr. X has bought the excellent report from Gartner “Market Share: Semiconductor Design Intellectual… Read More


Addressing MCU Mixed Signal Design Challenges

Addressing MCU Mixed Signal Design Challenges
by Daniel Payne on 04-09-2014 at 2:23 pm

The emerging market for IoT and wearable devices are designed with mixed-signal IP that includes: embedded CPU, flash, analogue and radio.EDA and IP companies have recently worked together to allow us to design an MCU with mixed-signal IP blocks more efficiently. This morning I attended a webinar with presenters from ARMand Read More


IP Reuse and Management in Monterey!

IP Reuse and Management in Monterey!
by Daniel Nenni on 04-08-2014 at 10:30 pm

One of the benefits of being part of SemiWiki is building relationships with a wide variety of companies covering every semiconductor design application imaginable. We are blessed, absolutely. Another benefit of being part of SemiWiki are the invitations to attend, participate, and even organize events such as EDPS. Last year… Read More


FinFET Custom Design

FinFET Custom Design
by Paul McLellan on 04-02-2014 at 8:30 pm

At CDNLive, Bob Mullen of TSMC gave a presentation on their new custom FinFET flow, doing design, and verifying designs. At 16nm there are all sorts of relatively new verification problems such as layout dependent effects (LDE) and voltage dependent design rules. We had some of this at 20nm but like most things in semiconductor,… Read More


Automating Analog Verification in Virtuoso

Automating Analog Verification in Virtuoso
by Daniel Payne on 03-31-2014 at 2:00 pm

Digital designers have been automating the functional verification process for many years now, however when you talk to an analog designer about how they do verification you quickly realize that the typical process is quite ad-hoc and little automated. Necessity does create an opportunity so the software engineers at MethodicsRead More


ARM, Cadence and the Internet of Things

ARM, Cadence and the Internet of Things
by Paul McLellan on 03-20-2014 at 6:30 pm

There is clearly a lot of hype about the Internet of Things (IoT) right now, but also it is clear that it will be a real market. In fact, it already is with various medical, fitness and home-appliance products already available. At CES in January, wearables was probably the biggest trend. That doesn’t always pan out (3D TV was… Read More


Cadence and ARM BFF

Cadence and ARM BFF
by Paul McLellan on 03-13-2014 at 6:38 pm

The biggest market for semiconductors is mobile and an ARM processor is the center of the axle around which it revolves. So everyone in the mobile ecosystem needs to work closely with ARM. At CDNLive earlier this week Cadence and ARM announced that they are deepening their partnership. Most of what they announced makes it a lot easier… Read More


Effective Verification Coverage through UVM & MDV

Effective Verification Coverage through UVM & MDV
by Pawan Fangaria on 03-10-2014 at 5:00 pm

In the current semiconductor design landscape, the design size and complexity of SoCs has grown to large extent with stable tools and technologies that can take care of integrating several IPs together. With that mammoth growth in designs, verification flows are evolving continuously to tackle the verification challenges … Read More


Automating PCB Timing Closure, Saving Up to 67%

Automating PCB Timing Closure, Saving Up to 67%
by Daniel Payne on 03-05-2014 at 10:10 am

The benefits of using EDA software is that it can automate a manual process, like PCB timing closure, saving you both time and engineering effort. This point was demonstrated today as Cadenceadded new timing-closure automation to their Allegroproduct family, calling it Allegro TimingVision. On Tuesday I spoke with Hemant ShahRead More


SoC Functional Verification Planning and Management Goes Big

SoC Functional Verification Planning and Management Goes Big
by Daniel Payne on 02-24-2014 at 10:01 am

Big SoC designs typically break existing EDA tools and old methodologies, which then give rise to new EDA tools and methodologies out of necessity. Such is the case with the daunting task of verification planning and management where terabytes of data have simply swamped older EDA tools, making them unpleasant and ineffective… Read More