Synopsys Expands Synopsys.ai EDA Suite with Full-Stack Big Data Analytics Solution

Synopsys Expands Synopsys.ai EDA Suite with Full-Stack Big Data Analytics Solution
by Kalar Rajendiran on 09-11-2023 at 10:00 am

Wafer Circuit Detail

More than two years ago, Synopsys launched its AI-driven design space optimization (DSO.ai) capability. It is part of the company’s Synopsys.ai EDA suite, an outcome of its overarching AI initiative. Since then, DSO.ai has boosted designer productivity and has been leveraged for 270 production tape-outs. DSO.ai uses machine… Read More


RISC-V 64 bit IP for High Performance

RISC-V 64 bit IP for High Performance
by Daniel Payne on 08-30-2023 at 10:00 am

Atrevido min

RISC-V as an Instruction Set Architecture (ISA) has grown quickly in commercial importance and relevance since its release to the open community in 2015, attracting many IP vendors that now provide a variety of RTL cores. Roger Espasa, CEO and Founder of Semidynamics, has presented at RISC-V events on how their IP is customized… Read More


AI and Machine Unlearning: Navigating the Forgotten Path

AI and Machine Unlearning: Navigating the Forgotten Path
by Ahmed Banafa on 08-16-2023 at 6:00 am

AI and Machine Unlearning Navigating the Forgotten Path

In the rapidly evolving landscape of artificial intelligence (AI), the concept of machine unlearning has emerged as a fascinating and crucial area of research. While the traditional paradigm of AI focuses on training models to learn from data and improve their performance over time, the notion of unlearning takes a step further… Read More


Breakthrough Gains in RTL Productivity and Quality of Results with Cadence Joules RTL Design Studio

Breakthrough Gains in RTL Productivity and Quality of Results with Cadence Joules RTL Design Studio
by Kalar Rajendiran on 08-08-2023 at 10:00 am

Joules RTL Design Studio Benefits

Register Transfer Level (RTL) is a crucial and valuable concept in digital hardware design. Over the years, it has played a fundamental role in enabling design of complex digital chips. By abstracting away implementation details and providing a clear description of digital behavior, RTL has contributed significantly to the… Read More


Cadence and AI at #60DAC

Cadence and AI at #60DAC
by Daniel Payne on 08-07-2023 at 10:00 am

Cadence, AI, #60DAC min

Paul Cunningham from Cadence presented at the #60DAC Pavilion and gave one of the most optimistic visions of AI applied to EDA that I’ve witnessed, so hopefully I can convey some of his enthusiasm and outright excitement in my blog report. Mr. Cunningham reviewed the various ages of EDA design with each era providing about… Read More


Qualitative Shift in RISC-V Targets Raises Verification Bar

Qualitative Shift in RISC-V Targets Raises Verification Bar
by Bernard Murphy on 08-02-2023 at 6:00 am

SVIPs

I had grown comfortable thinking about RISC-V as a cost-saving and more flexible alternative to Intel/AMD or Arm in embedded applications. Where clearly it is already doing very well. But following a discussion with Dave Kelf and Adnan Hamid of Breker, RISC-V goals have become much more ambitious, chasing the same big system applications… Read More


Wally Rhines Predicts the Future of AI at #60DAC

Wally Rhines Predicts the Future of AI at #60DAC
by Mike Gianfagna on 07-26-2023 at 10:00 am

Wally Rhines Predicts the Future of AI at DAC

Dr. Walden Rhines has appeared many times on SemiWiki. His discussions touch on a variety of topics, most recently on the health of EDA and IP. His knowledge of our industry is substantial, and he always seems to have a new take on the trends and technologies that are unfolding around us. So, when Wally took the stage for a keynote address… Read More


Reducing Electronic Systems Design Complexity with AI

Reducing Electronic Systems Design Complexity with AI
by Kalar Rajendiran on 07-20-2023 at 6:00 am

Siemens Reducing Complexity with AI Whitepaper Graphics

 

In the world of electronic systems design, complexity has always been a major challenge. As technology advances and demands for more efficient and powerful electronic devices grow, engineers face increasingly intricate design requirements. These complexities often lead to longer design cycles, increased costs, … Read More


Computational Imaging Craves System-Level Design and Simulation Tools to Leverage AI in Embedded Vision

Computational Imaging Craves System-Level Design and Simulation Tools to Leverage AI in Embedded Vision
by Kalar Rajendiran on 07-03-2023 at 10:00 am

Typical Pipelines

Aberration-free optics are bulky and expensive. Thanks to high-performance AI-enabled processors and GPUs with abundant processing capabilities, image quality nowadays relies more on high computing power tied to miniaturized optics and sensors. Computational imaging is the new trend in imaging and relies on the fusion … Read More


Alchip is Golden, Keeps Breaking Records on Multiple KPIs

Alchip is Golden, Keeps Breaking Records on Multiple KPIs
by Kalar Rajendiran on 05-10-2023 at 10:00 am

Alchip Revenue Breakdown along Nodes and Applications

I don’t know the story behind the name Alchip. I’ve been asking this question ever since its founding in 2003 and still haven’t found the answer. Wikipedia sometimes provides insights and stories behind names of companies, products and services but I couldn’t find any regarding the name Alchip. One thing is for sure. After its consistent… Read More