The incredible growth that the semiconductor industry has enjoyed over the last several decades is attributed to Moore’s Law. While no one argues that point, there is also industry wide acknowledgment that Moore’s Law started slowing down around the 7nm process node. While die-size reductions still scale, performance jumps… Read More
Standard Cell Scaling
Complex logic designs are built up from standard cells, in order to continue to scale logic we need to continually shrink the size of standard cells.
Figure 1 illustrates the dimensions of a standard cell.
Figure 1. Standard Cell Dimensions.
From figure 1 we can see that shrinking standard cell sizes requires… Read More
I was invited to give a plenary address at the SISPAD conference in September 2021. For anyone not familiar with SISPAD it is a premiere TCAD conference. This year for the first time SISPAD wanted to address cost and my talk was “Cost Simulations to Enable PPAC Aware Technology Development”.
For many years the standard in technology… Read More
Anyone who has read my previous articles about IEDM knows I consider it the premier conference on process technology.
Last year due to COVID IEDM was virtual and although virtual offers some advantages the hallway conversations that can be such an important part of the conference are lost. This year IEDM is returning as a live event… Read More
The big fake news last week came from a report out of China stating that TSMC won a big Intel order for 3nm wafers. We have been talking about this for some time on SemiWiki so this is nothing new. Unfortunately, the article mentioned wafer and delivery date estimates that are unconfirmed and from what I know, completely out of line. … Read More
Intel presented yesterday on their plans for process technology and packaging over the next several years. This was the most detailed roadmap Intel has ever laid out. In this write up I will analyze Intel’s process announcement and how they match up with their competitors.
10nm Super Fin (SF)
10nm is now in volume production in three… Read More
FinFETs devices are reaching their limits for scaling. Horizontal Nanosheets (HNS) are a type of Gate All Around (GAA) device that offers better scaling and performance per unit area. HNS is the logical next step from FinFETs because HNS processing is similar to FinFETs with a limited number of process changes required.
At the … Read More
At the 2021 Symposium on VLSI Technology and Circuits in June a short course was held on “Advanced Process and Devices Technology Toward 2nm-CMOS and Emerging Memory”. In this article I will review the first two presentations covering leading edge logic devices. The two presentations are complementary and provide and excellent… Read More
Recently, TSMC held their annual Technology Symposium, providing an update on the silicon process technology and packaging roadmap. This article will review the highlights of the silicon process developments and future release plans.
Subsequent articles will describe the packaging offerings and delve into technology … Read More
Over the recent years, the volume and velocity of discussions relating to chiplets have intensified. A major reason for this is the projected market opportunity. According to research firm Omdia, chiplets driven market is expected to be $6B by 2024 from just $645M in 2018. That’s an impressive nine-fold projected increase over… Read More
