Avoiding layout related variability issues

Avoiding layout related variability issues
by Daniel Nenni on 05-26-2013 at 7:55 am

In advanced process technologies, electrical and timing problems due to variability can become a big issue. Due to various processing effects, a circuit performance (both speed and power) is dependent on specific layout attributes and can vary a lot from instance to instance. The accumulated effects can be severe to the point… Read More


TSMC ♥ Solido

TSMC ♥ Solido
by Daniel Nenni on 04-27-2013 at 8:00 am

Process variation has been a top trending term since SemiWiki began as a result of the articles, wikis, and white papers posted on the Solido landing page. Last year Solido and TSMC did a webinar together, an article in EETimes, and Solido released a book on the subject. Process variation is a challenge today at 28nm and it gets worse… Read More


TSMC Responds to Samsung!

TSMC Responds to Samsung!
by Daniel Nenni on 04-12-2013 at 10:00 pm

This was the 19[SUP]th[/SUP] annual TSMC Symposium and by far the best I have attended. Finally tired of the misinformation that plagues our industry, TSMC set the record straight with wafer and silicon correlated data. TSMC shipped more than 88 MILLION logic wafers in 2012, more than any other semiconductor company, that gives… Read More


TSMC Tapes Out First 64-bit ARM

TSMC Tapes Out First 64-bit ARM
by Paul McLellan on 04-02-2013 at 2:15 am

TSMC announced today that together with ARM they have taped out the first ARM Cortex-A57 64-bit processor on TSMC’s 16nm FinFET technology. The two companies cooperated in the implementation from RTL to tape-out over six months using ARM physical IP, TSMC memory macros, and a commercial 16nm FinFET tool chain enabled by… Read More


FinFET Modeling and Extraction at 16-nm

FinFET Modeling and Extraction at 16-nm
by Daniel Payne on 12-18-2012 at 12:05 pm

In 2012 FinFET is one of the most talked about MOS technologies of the year because traditional planar CMOS has slowed down on scaling below the 28nm node. To learn more about FinFET process modeling I attended a Synopsys webinar where Bari Biswas presented for about 42 minutes include a Q&A portion at the end.


Bari Biswas, SynopsysRead More


TSMC OIP Forum 2012 Trip Report!

TSMC OIP Forum 2012 Trip Report!
by Daniel Nenni on 10-21-2012 at 6:00 pm

The second annual TSMC Open Integration Platform Ecosystem Forum was last week and let me tell you it was excellent. Great update on the TSMC process technology road maps, great for networking within the fabless semiconductor ecosystem, great for seeing what’s new in EDA and IP, and great for SemiWiki. It was time well spent for … Read More


Next Generation Transistors

Next Generation Transistors
by Paul McLellan on 04-27-2012 at 1:54 pm

We have all heard that planar transistors have run out of steam. There are two ways forward. The one that has garnered all the attention is Intel’s trigate which is their name for FinFET. The other is using thin film SoI which ST is doing. TSMC and Global seem to be going the FinFET way too, although at a more leisurely pace. But … Read More