Will TSMC be alone at 10nm and 7nm?!?!?

Now that the dust has settled let’s talk about the recent TSMC OIP Ecosystem Forum. This was the 6[SUP]th[/SUP] annual OIP which hosts more than 1,000 attendees from TSMC’s top customers and partners. Presenting this year were TSMC VP and CTO Dr. Jack Sun, TSMC VP of R&D Dr. Cliff Hou, and ARM EVP of Incubation Businesses Dr. Dipesh Patel. First let’s talk about some of the key manufacturing milestones that were mentioned.

Also read:Top 5 Highlights from the 2016 TSMC Open Innovation Platform Forum

TSMC announced that the new 16FFC process is currently in high volume manufacturing (HVM). As we know from the recent iPhone7 teardown the A10 SoC inside is TSMC 16FFC. Additionally, the new TSMC InFOs packaging is in HVM which is also used by Apple for the A10. The iPhone 7 teardown also showed that the majority of the chips inside the iPhone 7 are manufactured by TSMC including the Intel modem (TSMC 28nm) and the QCOM modem (TSMC 20nm). This represents a significant upside for TSMC in Q3 and Q4 of this year so get ready for some very upbeat investor calls.

TSMC announced that 10nm is ahead of schedule and will enter HVM in Q4 2016 versus Q1 2017. This supports my belief that the new Apple iPad A10x (to be announced next month) uses TSMC 10nm and will be the fastest SoC on the market, absolutely. I also believe that the next iPhone SoC (iPhone8) will use TSMC 10nm exclusively.

The chatter in the conference hall from people who would know was that due to unexpected yield challenges involving other 10nm processes, TSMC may be running unopposed at 10nm for the next 3-4 quarters. If so, this is huge for TSMC and the TSMC Ecosystem!

TSMC announced that 7nm is ahead of schedule and will start risk production in Q1 2017 meaning HVM will be Q4 2017 (just in time for the iPad A11x SoC). TSMC 7nm will use the same fabs as 10nm so the ramp will be predictably fast. This leaves TSMC again unopposed at 7nm for 1-2 years so congratulations to the hardworking people of TSMC.

And congratulations to TSMC partners and customers who will now lead the industry in semiconductor process development and will deliver industry leading chips for the rest of this decade. Just to name a few: Apple, ARM, Broadcom, MediaTek, Nvidia, Xilinx, etc…

Bottom line: TSMC has the strongest roadmap I have ever seen and will continue to dominate the foundry business for years to come (déjà vu 28nm).

The other interesting thing to note is that the 30 technical OIP presentations made by partners and customers are now available via TSMC Online:

Held Sept. 22th, 2016 at the Santa Clara Convention Center, the fifth TSMC’S Open Innovation Platform Ecosystem Forum was attended by more than 1,000 TSMC customers and the Open Innovation Platform design ecosystem partners from EDA, IP and Design Services. The Forum brought TSMC’s design ecosystem member companies together to share with our customers real-case solutions to customers’ design challenges and success stories of best practice in TSMC’s design ecosystem. In an adjacent Partner Pavilion, 50 design partner companies staffed booths, showcased their products and services, and took questions throughout the day from leading designers. 30 technical papers were presented during the forum, showing real solutions and how the complete OIP ecosystem achieves faster time to market.

Live EDA Technical Presentations:

• Timing Methodology for BEOL Variation (Qualcomm)
• 7 nm and the Dawn of Low-power, High-Performance Computing (Synopsys)
• Leveraging design house and foundry collaboration to drive power and area gains at leading-edge process nodes (MediaTek USA Inc.)
• HiSilicon Adopts Cadence Voltus IC Power Integrity Solution for 2.5D Interposer Design on TSMC Advanced CoWos Technology (HiSilicon / Cadence)
• Logic Design Co-Optimization (AMD)
• Circuit Reliability Success Story: HiSilicon usage of Calibre PERC (HiSilicon / Mentor Graphics)
• More Than Moore: A multi-die Touch Controller implementation (Synaptics)
• High-Performance CPU Core Implementation Using (ARM Cortex-A73) at 10nm with Cadence Implementation Flow (ARM / Cadence)
• NVIDIA Collaboration with TSMC and Synopsys on Extraction Flows for Advanced Node Designs (NVIDIA / Synopsys)
• Design and Verification of 16nm FFC Low Power SerDes for Datacenter and Automotive Applications (Mentor Graphics / Analog Bits)
  

Live IP Technical Presentations:

• Novel NeoFuse Based Random Number Seed Generator (eMemory)
• Meeting ADAS SoC Safety Design Challenges with Active Safety Features Built In to IP (Cadence)
• Low Power Mixed Signal on 16FFC (Analog Bits)
• Foundation IP for IoT and Mobile Applications on TSMC 40ULP (Synopsys)
• Achieving new performance heights with integrated memory subsystem and PHY architecture (Cadence)
• Making the Move from 28nm to 16nm FinFET – Easy as POP! (ARM)
• Enabling Smart Homes & Wearables with New Bluetooth IC Architectures on the proper technology nodes (Synopsys)
• The way to securely design a low-power SoC demonstrated on Silicon (Dolphin Integration)
• Software Driven Optimization for Performance, Power and Thermal Trade-Offs (Cadence)
• Automotive, IoT Driving New Semiconductor IP And Compliance Requirements (Synopsys)
  

Live Design Service Technical Presentations

• Design Challenge on MPHY G4 Receiver in TSMC 28HPC+ (M31 Technology)
• HBM IP Subsystem Implementation: 2.5D ASIC (Open-Silicon)
• Enabling Reliability, Quality and Safety within Automotive Design Platform (Synopsys)
• Power and Reliability Analysis of Next Generation Integrated Fan-out Wafer-level Packaging (ANSYS)
• Design, Simulation, and Verification of a Multi-Protocol SerDes (Silicon Creations)
• 7nm Custom/MS Reference Flow (Cadence)
• Enabling the Expanding Cloud: High Bandwidth Memory and 2.5D Solutions (eSilicon Corp.)
• Synopsys’ PrimeTime Advanced Low Power Signoff Technology (Synopsys)
• Gigachip Timing Closure in FinFET Process Node (Dorado Design Automation, Inc.)
• Functional Safety and Reliability Reference Flow for Automotive Applications (Cadence)

Print-Only Technical Presentations

• Integrated Solutions for TSMC InFO Designs (Cadence)
• Parasitic Challenges and Solutions Using Quantus QRC Extraction Solution for Advanced-Node FinFET Designs (Cadence)
• Design & Debug Your TSMC InFO Design Quickly and Accurately (Mentor Graphics)
• High Performance FinFET SRAM Design, Simulation, and Modeling (Synopsys)
• Using Convolutional Neural Networks in Image Recognition SoCs (Cadence)
• Embedded FPGAs for TSMC 40ULP Low-Power Applications (Flex Logix)
• A Game Plan to Deliver OTP in FinFET with New Challenges in Mixed-Signal Physical Design (Kilopass)
• On-chip ESD protection for 16nm FF+ (Sofics)
• MIPI in Automotive (Mixel)