As mentioned in previous blogs, design enablement is a key enabler to fabless semiconductor design and manufacture, without question. The purpose of this blog (in 500 words) is to compare and contrast two very different design enablement strategies and engage the semiconductor community in a meaningful discussion.
The GlobalFoundry strategy is straight forward so let’s start there. GFI is partnering with leading design enablement companies to advance semiconductor design at the 28nm node. GFI is committed to becoming the FIRST SOURCE for 28nm, competing directly with TSMC, while other foundries have in the past offered “T” like processes for 2[SUP]nd[/SUP] and 3[SUP]rd[/SUP] source manufacturing strategies (UMC, Chartered Semi, SMIC).
GFI is taking the sniper approach to partnerships rather than the traditional foundry business model of working with everybody (EDA, Semi IP, and Fabless ASIC companies). GFI has stated very clearly that they will not compete with partners and will in fact invest financially in the design enablement industry by purchasing products and services from said partners.
On the EDA side it is Synopsys for digital design, Cadence for AMS design, and Mentor for Verification and DFM. IP is ARM, Synopsys, Virage, and a collection of smaller companies. ASIC services is eSilicon, Open-Silicon, and SOCLE. Mask services is DNP, Hoya, and Tappan. I have heard that GFI has already cut millions of dollars of purchase orders with EDA and Semi IP companies. It would not surprise me at all if GFI is now the #1 customer of said partners so look for more GFI specific EDA tools, IP, and services in the coming quarters.
ARM, IBM, Samsung, GLOBALFOUNDRIES and Synopsys Announce Delivery of 32/28nm HKMG Vertically Optimized Design Platform
TSMC on the other hand has, over the last 10 years, implemented the shotgun approach to partnerships (TSMC Open Innovation Platform) which includes a “co-opetition” clause. Shotgun approach means TSMC works with EDA companies big and small, qualifying dozens of EDA tools and hundreds of silicon proven IP. Co-opetition means cooperative competition with partners via TSMC’s internal: IP development, mask services, and ASIC design services (Global Unichip Corp).
Two very different strategies, two very different outcomes?
Will GFI succeed in getting the 28nm 1[SUP]st[/SUP] source business? If 80% of foundry silicon is shipped by the top 20 fabless semiconductor companies is that your target market? Those top 20 companies are experts in semiconductor design enablement and do not need help with off the shelf tools and IP, what value can GFI really add there? And what about the 80% of the companies that ship 20% of the silicon? Can they really be ignored when one of them could easily be the next Cisco or Broadcom? What do you think?
Will TSMC invest more in the design enablement industry and compete less with partners? Can TSMC continue to take on all customers, big profit margin and small? TSMC has spent 100’s of millions of dollars on Semi IP, PDKs, and reference flows. Can that amount of spending continue to be justified? How do you think this will play out?
Answers to these questions will hopefully come in the form of comments so please share your opinions. The foundries and thousands of other people read my blog so lets hear it. In fact, more people read my blog than attended #47DAC!
Next week’s blog “TSMC versus GlobalFoundries: Semiconductor Design Enablement! II” will focus on feedback from TSMC and GFI executives. See you on Monday!Share this post via: