TSMC 2023 North America Technology Symposium Overview Part 2

The next topic I would like to cover is an update to the TSMC process node roadmap starting with N3. As predicted, N3 will be the most successful node in the TSMC FinFET family. The first version of N3 went into production at the end of last year (Apple) and will roll out with other customers in 2023. There is a reported record amount of N3x design starts in process and from what I have heard from the IP ecosystem, that will continue.

Not only is N3 easy to design to, the PPA and yield is exceeding expectations. While I’m hearing good things about N2 I still think the mainstream chip designers will stick to N3 for quite some time and the ecosystem agrees.

Meanwhile the competition is still working on 3nm. Intel 3 for foundry customers is still in process and Samsung 3nm was skipped by all. I still have not heard of a successful tape-out to Samsung 3nm from a customer name that I recognize.

Here are the TSMC N3 accomplishments from the briefing:

• N3 is TSMC’s most advanced logic technology and entered volume production in the fourth quarter of 2022 as planned; N3E follows one year after N3 and has passed technology qualification and achieved the performance and yield targets.
• Compared with N5, N3E offers 18% speed improvement at the same power, 32% power reduction at the same speed, a logic density of around 6X, and a chip density of around 1.3X.
• N3E has received the first wave of customer product tape-outs and will start volume production in the second half of 2023.
• Today, TSMC is introducing N3P and N3X to enhance technology values and offer additional performance and area benefits while preserving design rule compatibility with N3E to maximize IP reuse.
• For the first 3 years since inception, the number of new tape-outs for N3 and N3E is 5 to 2X that of N5 over the same period, because of TSMC’s technology differentiation and readiness.
• N3P: Offers additional performance and area benefits while preserving design rule compatibility with N3E to maximize IP reuse. N3P is scheduled to enter production in the second half of 2024, and customers will see 5% more speed at the same leakage, 5-10% power reduction at the same speed, and 1.04X more chip density compared with N3E.
• N3X: Expertly tuned for HPC applications, N3X provides extra Fmax gain to boost overdrive performance at a modest trade-off with leakage. This translates to 5% more speed versus N3P at drive voltage of 1.2V, with the same improved chip density as N3P. N3X will enter volume production in 2025.
• Today, TSMC introduced the industry’s first Auto Early technology on 3nm, called N3AE. Available in 2023, N3AE offers automotive process design kits (PDKs) based on N3E and allow customers to launch designs on the 3nm node for automotive applications, leading to the fully automotive-qualified N3A process in 2025.

TSMC N3 will be talked about for many years. Not only did TSMC execute as promised, the competition did not, so it really is a perfect semiconductor storm. The result being a very N3 focused industry ecosystem that will be impossible to beat, absolutely.

Here are the TSMC N2 accomplishments from the media briefing:

• N2 volume production is targeted for 2025; N2P and N2X are planned for 2026.
• Performance of the nanosheet transistor has exceeded 80% of TSMC’s technology target while demonstrating excellent power efficiency and lower Vmin, which is a great fit for the energy-efficient compute paradigm of the semiconductor industry.
  • TSMC has exercised N2 design collateral in the physical implementation of a popular ARM A715 CPU core to measure PPA improvement: Achieved a 13% speed gain at the same power, or 33% power reduction at the same speed at around 0.9V, compared to the N3E high-density 2-1 fin standard cell.
• Part of the TSMC N2 technology platform, a backside power rail provides additional speed and density boost on top of the baseline technology.
  • The backside power rail is best suited for HPC products and will be available in the second half of 2025.
  • Improves speed by more than 10-12% from reducing IR drop and signal RC delays.
  • Reduces logic area by 10-15% from more routing resources on the front side.

Remember, N2 is nanosheets, which, unlike FinFETs, is not open source technology so this is really going to be a challenge for design and the supporting ecosystem which gives TSMC a very strong advantage. TSMC also mentioned what follows nanosheets which I found quite interesting. I’m sure we will hear more about this at IEDM 2023:

• Transistor architecture has evolved from planar to FinFET and is about to change again to nanosheet.
• Beyond nanosheet, TSMC sees vertically stacked NMOS and PMOS, known as CFET, as one of the key process architecture choices going forward.
  • TSMC estimates the density gain would fall between 5 to 2X after factoring in routing and process complexity.
• Beyond CFET, TSMC made breakthroughs in low dimensional materials such as carbon nanotubes and 2D materials which could enable further dimensional and energy scaling.

For the record, TSMC has deployed 288 distinct process technologies and manufactured 12,698 products for 532 customers and counting. There is no stopping this train so you might as well jump on with the rest of the semiconductor industry.

Also Read:

TSMC 2023 North America Technology Symposium Overview Part 1

TSMC 2023 North America Technology Symposium Overview Part 3

TSMC 2023 North America Technology Symposium Overview Part 4

TSMC 2023 North America Technology Symposium Overview Part 5