The TSMC Symposium and OIP Ecosystem Fourm are the most coveted events of the year for the fabless semiconductor ecosystem, absolutely. In my 35 years of semiconductor experience never has there been a more exciting time in the ecosystem and that is clear by the overview and agenda for this year’s event. I hope to see you there:
The TSMC OIP Ecosystem Forum brings together TSMC’s design ecosystem companies and our customers to share practical, tested solutions to today’s design challenges. Success stories that illustrate TSMC’s design ecosystem best practices highlight the event.
More than 90% of last year’s attendees said that, “the forum helped me better understand TSMC’s Open Innovation Platform” and that “I found it effective to hear directly from TSMC OIP member companies.”
This year’s event will prove equally valuable as you hear directly from TSMC OIP companies about how to apply their technologies and joint design solutions to address your design challenges in High-Performance Computing (HPC), Mobile, Automotive and Internet-of-Thing (IoT) applications.
This year, the forum is a day-long conference kicking-off with trend-setting addresses and announcements from TSMC and leading IC design company executives.
The technical sessions are dedicated to 30 selected technical papers from TSMC’s EDA, IP, Design Center Alliance and Value Chain Aggregator member companies. And the Ecosystem Pavilion feature up to 70 member companies showcasing their products and services.
Date: Thursday, September 26, 2019 8:00 AM – 6:30 PM
Venue: Santa Clara Convention Center
Learn About:
- Emerging advanced node design challenges including 5nm, 6nm, 7nm, 12FFC/16FFC, 16FF+, 22ULP/ULL, 28nm, and ultra-low power process technologies.
- Updated design solutions for specialty technologies supporting Internet-of-Thing (IoT) applications
- Successful, real-life applications of design technologies and IP from ecosystem members and TSMC customers
- Ecosystem-specific TSMC reference flow implementations
- New innovations for next generation product designs targeting HPC, mobile, automotive and IoT applications
Hear directly from ecosystem companies about their TSMC-specific design solutions. Network with your peers and more than 1,000 industry experts and end users.
The TSMC Open Innovation Platform Ecosystem Forum is an “invitation-only” event. Please register to attend. We look forward to seeing you at the event.
The views expressed in the presentations made at this event are those of the speaker and are not necessarily those of TSMC.
Agenda:
Join the TSMC 2019 Open Innovation Platform® Ecosystem Forum and hear directly from TSMC OIP companies about how to leverage their technology to your design challenges!
08:00 – 09:00 Registration & Ecosystem Pavilion
09:00 – 09:20 Welcome Remarks
09:20 – 10:10 TSMC and its Ecosystem for Innovation
10:10 – 10:30 Coffee Break
REGISTRATION
Please click the paper title to see its abstract:
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HPC & 3DIC |
Mobile & Automotive |
IoT & RF |
| 10:30 – 11:00 |
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| 11:00 – 11:30 |
Calibre in the Cloud – A Case study with AMD, Mentor & TSMC
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| Microsoft/AMD/Mentor |
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Functional Safety Analysis and Verification to meet the requirements of the Automotive market
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| Texas Instruments/Cadence |
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Simplify Energy Efficient designs with cost-effective SoC Platform
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| Dolphin Design |
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| 11:30 – 12:00 |
Optimizing FPGA-HBM in InFO_MS Structure
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| Xilinx/Cadence |
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Thermal-induced reliability challenge and solution for advanced IC design
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| ANSYS |
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Flexible clocking solutions in advanced FinFET processes from 16nm to 5nm
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| Silicon Creations |
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| 12:00 – 13:00 |
Lunch & Ecosystem Pavilion |
| 13:00 – 13:30 |
Chiplets solutions using CoWoS and InFO with 112Gbps SerDes and HBM2E/3.2Gbps for AI, HPC and Networking
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| GUC |
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Overcome time-to-market and resource challenges: Hierarchical DFT for advanced node SoC design and production
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| AMD/Mentor |
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Developing AI-based Solutions for Chip Design
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| Synopsys |
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| 13:30 – 14:00 |
Realizing Adaptable Compute Platform for AI/ML and 5G with Synopsys’ Fusion Design Platform
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| Xilinx/Synopsys |
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Comprehensive ESD/Latch-up reliability verification for IP & SoC Designs
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| NXP/Silicon Frontline/Mentor |
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Reliable, Secure and Flexible OTP solutions in TSMC for IoT, AI and Automotive Applications
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| eMemory |
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| 14:00 – 14:30 |
HBM2E 4gbps I/O Design Techniques in 7nm & Below Nodes
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| Open-Silicon |
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Sensor fusion and ADAS SOC designs in TSMC 16FFC and N7
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| Cadence |
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High-Speed Interface IP PAM-4 56G/112G Ethernet PHY IP for 400G and Beyond Hyperscale Data Centers
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| Synopsys |
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| 14:30 – 15:00 |
Pushing 3GHz Performance of TSMC N7 Arm Neoverse N1 CPU using the Cadence Digital Flow
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| Cadence/Arm |
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AWS Cloud enablement of design characterization flows using Synopsys® Primetime® & HSPICE®
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| Xilinx/Synopsys |
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Automotive IP Functional Safety – A Verification Challenge
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| Cadence |
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| 15:00 – 15:30 |
Coffee Break & Ecosystem Pavilion |
| 15:30 – 16:00 |
Large Scale Silicon Photonic Interconnects for Mass Market Adoption
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| HPE/Mentor |
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A New Era of MIPI D-PHY and C- PHY: Automotive Applications
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| M31 |
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Best practices for Arm Cortex CPU energy efficient implementation flows
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| Arm |
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| 16:00 – 16:30 |
Photonics Coming of Age: From Laboratory to Mainstream Applications
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| Cadence/Lumerical |
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Integrating ADAS Controllers with Automotive-Grade IP for TSMC N7
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| Synopsys |
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The Challenges Posed by Dynamic Uncertainty on AI & ML Devices Targeting 16nm, 7nm & 5nm
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| Moortec |
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| 16:30 – 17:00 |
Accelerating Semiconductor Design Flows with EDA on the Cloud
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| Astera Labs/AWS |
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Arm automotive physical IP addresses new feature and functionality demands
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| Arm |
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Developing AI Accelerators for TSMC N7
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| Synopsys |
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| 17:00 – 17:30 |
Best Practices using Synopsys Fusion Technology to Achieve High-performance, Energy Efficient implementations of the latest Arm® Processors in TSMC 7nm FinFET Process Technology
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| Synopsys/Arm |
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Cloud-based Characterization with Cadence Liberate Trio Characterization Suite and Arm-based Graviton
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| Cadence |
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| 17:30– 18:30 |
Social Hour |
TSMC pioneered the pure-play foundry business model when it was founded in 1987, and has been the world’s largest dedicated semiconductor foundry ever since. The company supports a thriving ecosystem of global customers and partners with the industry’s leading process technology and portfolio of design enablement solutions to unleash innovation for the global semiconductor industry.
TSMC serves its customers with annual capacity of about 12 million 12-inch equivalent wafers in 2019 from fabs in Taiwan, the United States, and China, and provides the broadest range of technologies from 0.5 micron plus all the way to foundry’s most advanced processes, which is 7-nanometer today. TSMC is the first foundry to provide 7-nanometer production capabilities, and is headquartered in Hsinchu, Taiwan.
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