TSMC Responds to Samsung!

This was the 19[SUP]th[/SUP] annual TSMC Symposium and by far the best I have attended. Finally tired of the misinformation that plagues our industry, TSMC set the record straight with wafer and silicon correlated data. TSMC shipped more than 88 MILLION logic wafers in 2012, more than any other semiconductor company, that gives them significant bragging rights which they rarely exercise. It was standing room only (I counted 1,200+ chairs) not including the 48 ecosystem partner companies manning the booths next door.

The one thing that was not mentioned was the Apple move from Samsung to TSMC starting at 20nm. Considering Apple is responsible for an estimated 70% of Samsung’s foundry business this product shift is devastating. Several ecosystem partners told me that Samsung is cutting budgets for their ecosystem (tools and IP) in preparation for the Apple loss. TSMC on the other hand has 850 people building their ecosystem with an annual shared budget of $1.5B. This ecosystem delivers silicon accurate tools, reference flows, and IP blocks (5k+) for each and every process node. The Chairman (Dr. Morris Chang) calls this, appropriately enough, the Grand Alliance! Interesting notes from the Chairman:

• Semiconductor industry contracted 2-3% in 2012
• TSMC customers outperformed the PHLX Semiconductor Sector (SOX)
• Semiconductor industry to grow 4% in 2013
• Fabless companies will grow 9% in 2013
• TSMC will grow “in the teens” again in 2013 (TSMC grew 19% in 2012)

One thing you have to realize about mobile SoCs is that they only have a one year shelf life. The most recent Samsung based Apple A6 SoC will die a very quick death when the TSMC based A7 starts shipping next year. This is a new experience for us as semiconductor professionals. This is changing the way we buy and sell wafers. Don’t get me wrong, price will always be important but the mobile customers also buy technology road maps: What can be delivered when, at what capacity, and at what confidence level. It’s all about setting customer expectations and exceeding them and that was the focus of this symposium.

Dr. Jack Sunreminded us that TSMC is the only foundry to successfully ramp 28nm according to the road maps. 20nm is ramping now three months ahead of schedule and 16FF will start to ramp next year which is half the time it usually takes between nodes. This correlates to what I blogged about before with “Wrights Law” which states that “We learn by doing” or that the cost of a unit decreases as a function of the cumulative production. Other interesting notes:

• 20nm is ahead of schedule (production starting in 2013)
• 16nm FF is yielding ahead of plan based on 128MB SRAM test chip data
• 10nm FF is in process with a 2[SUP]nd[/SUP] generation FinFET (GePMOS)
• COWOS is in production with multiple tape-outs @ > 95% yield

Dr. Cliff Hou talked about the design challenges from 65nm (low power), 40nm (HKMG), 20nm (double patterning), 16nm (FinFets), and 10nm (multi patterning and spacer). Cliff is a great speaker, very smart, and very personable. If I had to pick the next TSMC CEO it would be Cliff. The most interesting slide he presented for me was the design rule comparisons per node:

• 700 rules @ 90nm
• 800 rules @ 65nm
• 1,200 rues @ 40nm
• 1,900 rules @ 28nm
• 3,000 rules @ 20nm
• 3,400 rules @ 16nm

Now look at the DRC deck size comparisons per node:

• Just under 20,000 @ 90nm
• Just over 20,000 @ 65nm
• Just under 30,000 @ 40nm
• Just over 40,000 at 28nm
• Right on 80,000 at 20nm
• Just under 100,000 @ 16nm

Using this data and a very complex algorithm would put 10nm rules at 5,000 and DRC deck size at 250,000. Are we really prepared for this kind of complexity with our current DRMs in PDF formats?

J.K. Wangfollowed Cliff with some very interesting data on building fabs. Paul McLellan did a nice blog on it already: How Long Does it Take to Go From a Muddy Field to Full 28nm Capacity? J.K. is one of the original TSMC employees so you can bet he can build a fab.

If I had to sum up the conference in one sentence here it is:

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