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Taiwan Semiconductor Manufacturing Corporation (NYSE: TSM)

Taiwan Semiconductor Manufacturing Corporation (NYSE: TSM)
by Daniel Nenni on 07-11-2010 at 10:09 pm
Categories: Foundries, TSMC

After working with TSMC the past 10+ years the single most compelling question I have is why the stock (NYSE: TSM) is not at record highs. TSMC invented and continues to dominate the foundry business which is clearly the future of modern semiconductor design and manufacture. So why is this not a $20+ stock?!?!?

TSMC reports 36%+ net margins.
TSMC delivers a 24%+ return on equity.
TSMC just announced a 3.8% dividend.
TSMC carries $6B+ total cash.
TSMC has more capacity than its top rivals combined and a third Gigafab under construction.
TSMC has almost a 7X Market Cap margin between its closest rival UMC.
So why is TSM flatlining after yet another record setting month of sales?!?!?

One of my favorite stock crowdsourcing groups agrees that TSM is undervalued. Based on the aggregate intelligence of 165k+ investors participating in Motley Fool CAPS, TSMC has a 5 out of 5 star rating. A Motley Fool CAPS rating indicates a stock’s potential to outperform the S&P 500 as determined by the community. On CAPS, 99% of the 437 All-Star members who have rated Taiwan Semiconductor Manufacturing Corporation believe the stock will outperform the S&P 500 moving forward.

Just how strong is TSMC in the global semiconductor foundry business? Well, with 45%+ market share, TSMC is about three times as big as its closest competitor, #2 foundry UMC, and more than six times as big as the #4 China based foundry SMIC. Even with the overly documented 40nm yield ramping problems, TSMC is still in charge of that node with an estimated 80% market share. Today, the race for 28nm is on with production silicon due out in Q1 2011. TSMC? GlobalFoundries? Samsung? It’s a 3 horse race, expect a photo finish, the winner is the King of the Node!

TSMC is expected to finish 2010 at $12.5B.
TSMC serves the largest and most diverse customer base.
TSMC will spend a record $4.8B on capital expansion this year.
TSMC will be trying to recruit 5,000 new employees this year.
TSMC is investing heavily in LED and Solar thin film PV technologies.
TSMC is the favorite to win the 28nm node foundry race next year.
TSMC has a 5 star Motley Fool CAPS rating.

Out of control consumer spending will continue to drive foundry revenues to record highs. Semiconductor industry mystics see foundry revenue growing 30-40% in 2010 and 8-10% annually over the next 4 years. Meanwhile, in 2010 shares of TSM and UMC are down 12% and 21%, respectively. So tell me again why TSM is yet another under performing tech stock?!?!

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TSMC Unveils First Ever AMS Reference Flow!

TSMC Unveils First Ever AMS Reference Flow!
by Daniel Nenni on 06-08-2010 at 9:17 pm
Categories: EDA, Foundries, TSMC

As a quick follow-up to my blog TSMC Extends Open Innovation Platform, TSMC today announced the Analog/Mixed Signal Reference Flow 1.0., another key collaborative component of TSMC’s Open Innovation Platform™.

The TSMC AMS Design Flow 1.0’s design package is integrated seamlessly on top of the 28nm interoperable process design kit (iPDK) and OpenAccess database and includes:

  • Industry-first layout-dependent effect (LDE) aware design methodology
  • TSMC-specific LDE engine
  • Complete DFM-aware analog layout guideline and checker utility
  • Advanced analog base cell (ABC) design
  • Comprehensive design configuration management environment
  • A robust front-end design and simulation platform for the analysis of design sensitivity, yield, multi process corners, noise effect, IR drop and electromigration (EM) issues.
  • Constraint-driven analog placement and routing technology for fast layout prototyping, semi-automatic rule-driven layout assistance, and a demonstration of a PLL system design budgeting and loop filter layout synthesis capability.
  • A Physical verification flow that includes accurate 3D field solver based extraction with intelligent RC reduction, and full DRC/LVS sign-off and dummy pattern insertion and extraction.


“TSMC’s Open Innovation Platformdeliverscomprehensive and innovative designtechnology services that remove advanced technology adoption barriers. Ithelpslower design costs andimprovestime-to-market,” said Dr Fu-Chieh Hsu, Vice President of Design Technology Platform and Deputy Head of Research & Development. “TheOpen Innovation Platform willnow beginaddressing system-level design’s cost and complexity and enable packaging of entire electronic systems onto multi-chip packages.”

The TSMC AMS Reference Flow 1.0 is developed and fully validated in collaboration with multiple EDA partners including:

  • Apache Design Solutions
  • Berkeley Design Automation
  • Cadence
  • Ciranova
  • EdXact
  • Mentor Graphics
  • Magma Design Automation, Mentor
  • Pyxis Technology
  • Silicon Frontline
  • SpringSoft
  • Solido Design Automation
  • Synopsys

“The design ecosystem must move beyond its current bounds and embrace the systems- level challenges that are at the heart of every design consideration. The Open Innovation Platformbegan setting the standard for ecosystem collaboration two years ago. TSMCcontinues to answer the market’s calland will build that same collaborative spirit on a system-level basis,” explained S.T. Juang, senior director, Design Infrastructure Marketing at TSMC.

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TSMC Extends Open Innovation Platform

TSMC Extends Open Innovation Platform
by Daniel Nenni on 06-07-2010 at 9:24 pm
Categories: EDA, Foundries, TSMC

TSMC today extended one of the most effective semiconductor design enablement initiatives the semiconductor world has ever seen, the Open Innovation Platform (OIP). Morris Chang coined the term “OIP” himself in 2008, but the effort itself is 10+ years old with a collective cost > .5B$. My other blogs on topic include: TSMC OIP vs CDNS OIP Analysis, TSMC Open Innovation Platform Explained, andTSMC iPDK Debate.

The Open Innovation Platform’s global EcosystemAllianceprograms have grown to include 30 EDA partners, 38 IP partners, 23DesignCenterAlliance(DCA) partners, and 9 Value Chain Aggregator (VCA) partners. All partners participate in one or more of the Open Innovation Platform collaboration programs. TSMC also begins to work collaboratively with industry organizations, such as IPL Alliance and Si2, to promote the interoperability standards based on TSMC interoperable EDA formats.

Impressive! But is TSMC the #1 semiconductor foundry because of their design enablement activities? Or is this design enablement initiative #1 because TSMC is the industry leading foundry?

I like the executive quotes included in the official TSMC press release, they speak volumes:

“The electronic design community is embracing the EDA360 vision to enable fastest approach from concept to consumer and together with IP suppliers, EDA vendors and silicon manufacturers, we have diligently collaborated to build a cohesive path for designers,” said Lip-Bu Tan, president and chief executive officer, Cadence. “TSMC’s Open Innovation Platform is a proven, integral part of this path. TSMC’s Open Innovation Platform will now make significant advancements in low-power, mixed-signal, system-level and 3D-IC design to enable further productivity improvements that our mutual customers need.”


News flash: The semiconductor community has NOT embraced EDA360. Just because you keep saying something over and over does not make it true, especially when it is self serving. I have spoken to dozens of semiconductor industry professionals and the foregone conclusion is that EDA360 is aNothing Burger!


“Going forward,Mentor and TSMC are developing complete solutions for the TSMC design ecosystem, ” said Walden C. Rhines, Chairman and CEO,Mentor Graphics. “The TSMC OIP effort is not just words — theMentor Track in Reference Flow 11.0, and the co-developed iDRC and iLVS languages, are real usable results.”

I like Wally’s style here, say more with less. My lunch with Wally is next week so hopefully I can get him to say more on the subject.

“Collaboration across the entire design eco-system — customers, foundries, IP and EDA suppliers — is critical for lower design risk and cost, better power and performance, and customer differentiation, ” said Aart de Geus, Chairman and CEO, Synopsys. “The new technologies in this phase of TSMC OIP, such as system-level design, analog/mixed-signal (AMS) design and thru-silicon-via, bring key solutions to speed System-to-IC realization.”

Aart is pointing out that the TSMC OIP not only competes directly with the Cadence EDA360 OIP, it plays to the strengths of Synopsys. In fact, the EDA360 Manifesto highlights the strengths of both Mentor and Synopsys: System Realization, SoC Realization, and Silicon Realization. Synopsys and Mentor own EDA360.

The most interesting quote, or lack there of, is from Magma CEO Rajeev Madhaven. Seriously, Magma is an integral part of the TSMC OIP expansion but no quote from Rajeev? I would like to think it is a conspiracy against Magma by the top 3 EDA CEO’s as a result of Magma’s business practices, but I’m sure there is a far less interesting explanation.

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TSMC versus GlobalFoundries: Semiconductor Design Enablement!

TSMC versus GlobalFoundries: Semiconductor Design Enablement!
by Daniel Nenni on 06-01-2010 at 9:00 pm
Categories: EDA, Foundries, GlobalFoundries, IP, TSMC


As mentioned in previous blogs, design enablement is a key enabler to fabless semiconductor design and manufacture, without question. The purpose of this blog (in 500 words) is to compare and contrast two very different design enablement strategies and engage the semiconductor community in a meaningful discussion.

The GlobalFoundry strategy is straight forward so let’s start there. GFI is partnering with leading design enablement companies to advance semiconductor design at the 28nm node. GFI is committed to becoming the FIRST SOURCE for 28nm, competing directly with TSMC, while other foundries have in the past offered “T” like processes for 2[SUP]nd[/SUP] and 3[SUP]rd[/SUP] source manufacturing strategies (UMC, Chartered Semi, SMIC).

GFI is taking the sniper approach to partnerships rather than the traditional foundry business model of working with everybody (EDA, Semi IP, and Fabless ASIC companies). GFI has stated very clearly that they will not compete with partners and will in fact invest financially in the design enablement industry by purchasing products and services from said partners.

On the EDA side it is Synopsys for digital design, Cadence for AMS design, and Mentor for Verification and DFM. IP is ARM, Synopsys, Virage, and a collection of smaller companies. ASIC services is eSilicon, Open-Silicon, and SOCLE. Mask services is DNP, Hoya, and Tappan. I have heard that GFI has already cut millions of dollars of purchase orders with EDA and Semi IP companies. It would not surprise me at all if GFI is now the #1 customer of said partners so look for more GFI specific EDA tools, IP, and services in the coming quarters.

ARM And GLOBALFOUNDRIES Establish A Strategic Partnership To Enable Application-Optimized SOC Products On 28NM Highk Metal Gate (HKMG) Process

GLOBALFOUNDRIES Releases Industry’s First Silicon-Validated Library for Pattern-Based SoC DFM Verification at 28nm and Below

ARM, IBM, Samsung, GLOBALFOUNDRIES and Synopsys Announce Delivery of 32/28nm HKMG Vertically Optimized Design Platform

TSMC on the other hand has, over the last 10 years, implemented the shotgun approach to partnerships (TSMC Open Innovation Platform) which includes a “co-opetition” clause. Shotgun approach means TSMC works with EDA companies big and small, qualifying dozens of EDA tools and hundreds of silicon proven IP. Co-opetition means cooperative competition with partners via TSMC’s internal: IP development, mask services, and ASIC design services (Global Unichip Corp).

Two very different strategies, two very different outcomes?

Will GFI succeed in getting the 28nm 1[SUP]st[/SUP] source business? If 80% of foundry silicon is shipped by the top 20 fabless semiconductor companies is that your target market? Those top 20 companies are experts in semiconductor design enablement and do not need help with off the shelf tools and IP, what value can GFI really add there? And what about the 80% of the companies that ship 20% of the silicon? Can they really be ignored when one of them could easily be the next Cisco or Broadcom? What do you think?

Will TSMC invest more in the design enablement industry and compete less with partners? Can TSMC continue to take on all customers, big profit margin and small? TSMC has spent 100’s of millions of dollars on Semi IP, PDKs, and reference flows. Can that amount of spending continue to be justified? How do you think this will play out?

Answers to these questions will hopefully come in the form of comments so please share your opinions. The foundries and thousands of other people read my blog so lets hear it. In fact, more people read my blog than attended #47DAC!

Next week’s blog “TSMC versus GlobalFoundries: Semiconductor Design Enablement! II” will focus on feedback from TSMC and GFI executives. See you on Monday!

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TSMC OIP vs CDNS OIP Analysis

TSMC OIP vs CDNS OIP Analysis
by Daniel Nenni on 05-28-2010 at 9:04 pm
Categories: EDA, Foundries, TSMC

Launched in April 2008, the TSMC OIP initiative is a collaborative strategy aimed at breaking down the barriers of semiconductor design enablement in order to reduce waste and increase the profitability of the industry as a whole.

The TSMC Open Innovation Platform promotes timeliness-driven innovation amongst the semiconductor design community, its ecosystem partners and TSMC’s IP, design implementation and DFM capabilities, process technology and backend services. The Open Innovation Platform™ includes a set of ecosystem interfaces and collaborative components initiated and supported by TSMC that efficiently empowers innovation throughout the supply chain and enables the creation and sharing of newly created revenue and profitability.

The TSMC OIP targets include the following areas of inefficiencies:

[LIST=1]

  • PDKs: the iPDK standard is innovation driven versus format driven.
  • EDA Reference Flows and tool qualification, verified design sign-off flows.
  • TSMC IP portal: documenting silicon proven IP from both TSMC and commercial IP vendors such as Virage Logic.
  • TSMC collaborative services.The annual TSMC OIP conferences are stocked with top semiconductor, EDA, and IP executives from around the world. The keynotes, panels, and discussions are highly interactive, the format and content is truly collaborative and exactly what our industry needs to scale and move forward in a profitable manner.

    A new entry to this format is the Cadence Open Integration Platform launched inside the infamous EDA360 Manifesto. As they say, identify theft is the sincerest form of flattery:

    Cadence Design Systems, Inc. (NASDAQ: CDNS), the global leader in EDA360, today announced the Cadence Open Integration Platform, a platform that significantly reduces SoC development costs, improves quality and accelerates production schedules. A key pillar in support of its EDA360 vision for next-generation application-driven development, the Cadence Open Integration Platform comprises integration-optimized IP from the company and its ecosystem participants…

    The goal of both OIP’s is obvious, to reduce waste within the semiconductor design and manufacture process. People in this industry are accustomed to waste, business as usual, so this is a significant challenge! A former co-worker, Jack Harding CEO of eSilicon, estimates a 20% SoC design waste due to inefficiencies including lack of process node design experience. I say it is closer to 30% if you include the SoC mortality rate. 20-30% of the $50-100M SoC “realization” cost is a significant amount, especially if you are borrowing the money from a VC.
    The result of my expert analysis in the case of TSMC OIP versus CDNS OPI is based on the definition of the word:

    col·lab·o·ra·tion    –noun

    1. the act or process of collaborating.

    2. a product resulting from collaboration: This dictionary is a collaboration of many minds.

    TSMC follows the academic definition as the key to the fabless semiconductor design and manufacturing business is collaboration. Transforming a closed (IDM) design and manufacture process into a truly open semiconductor foundry business is an amazing thing and TSMC clearly has earned the title “Global Leader in Fabless Semiconductor Design and Manufacture”.
    CDNS brings a new definition to the word collaboration by alienating (opposite of collaborating) key partners in the ecosystem:

    [LIST=1]

  • Process pioneering foundries and semiconductor manufacturing equipment companies (EDA360 says new process nodes are scary so you should stay at older nodes as long as possible.)
  • EDA and IP Bretheren. (Cadence is the self appointed “Global Leader of EDA360”, which is nothing more than the repackaging of existing technology with a big public relations bow on it.)
  • Customers. ( Is this not deja vu of the arrogant behavior during the Cadence Fister/Intel era? Ditching DAC, cutting partner programs, etc…)
    In the hands of the EDA Consortium (EDAC), EDA360 would be a brilliant blueprint for the EDA industry and could easily replace “Where Electronics Begins”. Unfortunately, in the hands of Cadence it will not. My bet is that CDNS EDA360 will in fact be John Bruggeman’s Waterloo and CDNS OIP will be renamed or will die a silent death. Just my opinion of course, but I am the Global Leader of Independent Semiconductor Bloggers.
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450mm Semiconductor Manufacturing Debate

450mm Semiconductor Manufacturing Debate
by Daniel Nenni on 05-23-2010 at 2:39 pm
Categories: Foundries, TSMC


This blog posting is sponsored by EVA airlines, as I’m in the EVA executive lounge eating free food (I blog for food). “Fly EVA, the lesser of evils for Taiwan air travel!” EVA Air has a perfect safety record in 9 years of operation, China Air on the other hand has the worst safety record in the industry!

This blog was inspired by one of the longest, most spirited discussions I have read on a LinkedIn semiconductor group. A question posted on the Semiconductor Professionals Group five months ago, starting with a simple question, “Any status of 450mm? Who will be adopting first?”. It is followed by 160+ comments from semiconductor experts around the world.

TSMC, Intel, Toshiba, and Samsung all support the transition to 450mm citing both important technological advancements as well as significant capacity increases to meet the needs of future smartphone users around the world. One 450mm wafer should yield more than twice as much compared to today’s 300mm, and well over four times the number from yesterday’s 200mm.

Unfortunately, the semiconductor equipment manufacturers, the enablers of 450mm wafers, lost more than $1B and released 30%-40% of their workforces in 2009. Once scheduled for a 2012 launch, the transition to 450mm wafers has been delayed due to the financial meltdown. But with the current semiconductor industry upswing with foundries like TSMC and UMC operating at maximum capacity, the 450mm debate continues.
The debate about 450mm really boils down to: Will 450mm increase total capacity while reducing manufacturing costs? And is 450mm the best way to accomplish this?

According to Thomas Sonderman, Vice President of manufacturing systems and technology at GlobalFoundries:

“The rush to 450mm suggests a lack of ideas for improving fab productivity. At GlobalFoundries, we see a tremendous amount of headroom left in the 300mm process. We are tapping our expertise in lean manufacturing to extend the lifecycle of the industry’s current 300mm investments, and we are investing more than $4 billion in a new, state-of-the-art 300mm fab in upstate New York because we are confident in our ability to get the most out of this technology generation.”

The key to GLOBALFOUNDRIES “lean manufacturing” is a model based on highly automated decision-making called Automated Precision Manufacturing (APM). APM was a key technology that enabled AMD to compete as an IDM, which GlobalFoundries is now offering to a broader base of customers as a foundry.

According to Jack Sun, Vice President, Research and Development and Chief Technology Officer at TSMC:

“A move to 450mm is important for cost reduction and I believe it’s going to happen. The device manufacturers and governments all have to pitch in and contribute to the effort. People will find a way to invest so that we can deliver 450mm. Before the credit crunch, the target was 2012. It has moved out a couple of years, it has pushed out to the middle of this decade.”
In the early days of semiconductor, the device manufacturers themselves produced the required tools and equipment. That could easily come full circle with 450mm. With a limited amount of potential customers and under staffed and under funded semiconductor manufacturing equipment companies, Intel, Samsung, TSMC, and Toshiba, may be forced to develop 450mm manufacturing tools and machinery. TSMC already has 450nm enabling equipment in-house for R&D, alpha, and beta testing. Intel, Toshiba and Samsung may have internal 450mm development activities as well.

According to Daniel Nenni, famed semiconductor blogger:

“450mm manufacturing capabilities will separate the men from the boys. If Samsung (Korea) is the only memory manufacture with 450mm capabilities, Micron (USA), Toshiba and Elpida (Japan), and Taiwan Memory, will be dog food. If TSMC (Taiwan) is the only foundry with 450mm manufacturing capabilities, TSMC will be the Great Dane of the semiconductor world!”

lang: en_US

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2010 Semiconductor Foundry Update: Consolidation!

2010 Semiconductor Foundry Update: Consolidation!
by Daniel Nenni on 05-16-2010 at 6:46 pm
Categories: Foundries, GlobalFoundries, TSMC

It has been an interesting month in the semiconductor business. Record revenues, profits, aggressive expansion plans, something we have not seen before and may not see again. Let’s start in Taiwan then move to Silicon Valley, Upstate New York, China, and Korea, with a look at: financials, capacity, and consolidation.

TSMC and UMC both posted record sales and profits exceeding even the optimistic. The top semiconductor companies followed suit which prompted the often quoted market researcher iSuppli to predict the chip industry is set for its highest annual growth in a decade: Semiconductor sales will climb to an all-time high of $300 billion in 2010, up from $230 billion last year. The previous sales record was $274 billion in 2007. According to iSupply, the last time semiconductor sales increased at such a rate was in 2000 when sales grew at 36.7%.

Though the semiconductor industry is estimated to grow 30%+ in 2010, TSMC and the foundry business is heading for much higher growth. Both fabless and fabbed semiconductor companies are reserving capacity with TSMC to ensure their SoCs hit the market window, compounding the wafer allocation problem that started earlier this year.

Capacity of course is key to semiconductor riches and will play the most significant role in who will deliver silicon to future generations. During my last visit to Taiwan, friends from TSMC briefed me on the Gigafab concept to which TSMC has publicly committed billions of dollars in capital expenses. A third $3B+ Gigafab will be constructed in the central Taiwanese city of Taichung and is slated to go online by the end of 2011. Nobody brings a new fab online faster and cheaper than TSMC, believe it.

While capitol spending is the key indicator of organic capacity growth, inorganic growth is also high on the foundry agenda: GlobalFoundry’s acquisition of Chartered Semiconductor, UMC’s investment in China’s He Jian, and TSMC’s equity stake in SMIC. GlobalFoundries clearly understands that capacity is everything in the foundry business, also understanding that they are no match for TSMC in a Fab building contest. Look for more inorganic growth for GlobalFoundries.

One of the leading semiconductor crystal ball sites predicted that there will only be three semiconductor manufacturers producing wafers below 20nm. It has been repeated so many times I don’t remember where it came from but now some view it as a truth. Today there are six foundries pushing Gordon Moore’s Empirical Observation: TSMC, UMC, GlobalFoundries, SMIC, Samsung, and IBM. That could certainly consolidate down to three: TSMC, Samsung, and GlobalFoundries.

While capitol spending is the key indicator of organic capacity growth, inorganic growth is also high on the foundry agenda: GlobalFoundry’s acquisition of Chartered Semiconductor, UMC’s investment in China’s He Jian, and TSMC’s equity stake in SMIC. GlobalFoundries clearly understands that capacity is everything in the foundry business, also understanding that they are no match for TSMC in a Fab building contest. Look for more inorganic growth for GlobalFoundries.

One of the leading semiconductor crystal ball sites predicted that there will only be three semiconductor manufacturers producing wafers below 20nm. It has been repeated so many times I don’t remember where it came from but now some view it as a truth. Today there are six foundries pushing Gordon Moore’s Empirical Observation: TSMC, UMC, GlobalFoundries, SMIC, Samsung, and IBM. That could certainly consolidate down to three: TSMC, Samsung, and GlobalFoundries.

lang: en_US

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TSMC Earthquake Damage Redo

TSMC Earthquake Damage Redo
by Daniel Nenni on 04-14-2010 at 10:54 pm
Categories: Foundries, TSMC

As you may know I enjoy poking fun at the current state of semiconductor design and manufacture media; sloppy reporting, editors with little or no actual semiconductor experience taking corporate marketing spins on news/events and passing it along as fact.

Last week it was the EETimes parroting the Samsung foundry business press. A nice thing about being a blogger and owning your own domain is that you get to see (Google Analytics) where the views come from and which links they click on etc…. It’s like spying on your siblings, not that I ever did that. Lets just say that last week South Korea discovered my blog.

This time it is the ElectronicsWeakly top viewed article TSMC Loses 40K Wafers In Quake by one of my fellow bloggers David Manners. There was a lot of press on this topic last week but David is the only one to put a number (40,000 wafers, which is significant) on the loss, and he led with it in an article versus his blog (insert sinister music here). The question is: Where did David get a 40,000 wafer loss number? Certainly not from the official TSMC press brief:

TSMC Reports Impact From March 4 Earthquake Initial Estimate of 1.5 Days Wafer Movement Loss
Issued by: TSMC Issued on: 2010/03/04 Hsinchu, Taiwan, R.O.C. – March 4, 2010 – TSMC (TWSE: 2330, NYSE: TSM) today announced that an earthquake of magnitude 6.4 on the Richter scale occurred in south Taiwan at 8:18 am Taiwan local time on March 4. The earthquake registered on instruments at TSMC’sTainansite at magnitude 5, and was measured at TSMC’s Hsinchu site at magnitude 2.

Current assessments reports show that the earthquake had minimal impact on Hsinchu fabs. WhileTainan fabs suffered greater impact, they have gradually begun to resume production. Our initial estimate is that the earthquake caused the equivalent of 1.5 days loss of wafer movement for the company in total.

Luckily one of my siblings, that I absolutely did not spy on when I was a kid, spent his career with semiconductor equipment manufacturers and knows of such things. He says that determining actual wafer or die loss in this context is next to impossibleand here is why:

There are 300+ steps in wafer production so the impact is spread over a long wafer movement process.Average wafer movement loss is calculated as: Each Fab’s Equipment Production Time Loss (including equipment check and recalibration) + Each Fab’s Wafer Scrap (wafers removed from the movement process and not returned) / by over all wafer movement for the company (TSMC). Average wafer movement loss is expressed in “days loss of wafer movement”, which is an averaged manufacturing index, not an actual wafer scrap or revenue loss number. Bottom line, you can’t determine actual “lost wafers” from “loss of wafer movement”.

It looks like David took TSMC’s 2009 capacity of 9,995,000 8-in wafers (the 8-in. equivalent number is used to normalize 6,8, and 12-in. wafer production) and divided it out using 1.5 days of “wafer movement loss” as “lost wafer production”. My emails to David on the subject were not returned. Even funnier, I was in Taiwan that week. Funny because my Taiwan friends accuse me of bringing earthquakes with me from California. As I blogged last year, I was in Taiwan for both the July 2009 and the September 1999 earthquakes, also typhoons and an airplane crash. Pure coincidence I assure you.

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Redefining the Semiconductor Foundry Model: Abu Dhabi versus Taiwan

Redefining the Semiconductor Foundry Model: Abu Dhabi versus Taiwan
by Daniel Nenni on 04-11-2010 at 2:53 pm
Categories: EDA, Foundries, GlobalFoundries, Siemens EDA, TSMC

It was a pleasure to see the GlobalFoundries (GFI) corporate pitch at the Mentor Graphics U2U Conference last week. Wally Rhines is a tough act to follow but Mojy Chian, Senior Vice President of Design Enablement at GlobalFoundries, presented a compelling argument for a refined foundry business model. The GFI people were also nice enough to send the presentation, offer a private briefing, and honor my request for a picture of an actual 28nm test chip wafer.

I first met Mojy Chian at Conexant and again at Altera where he was Vice President of Technology managing development, infrastructure, and manufacturing (down to TSMC 40nm). I last met Mojy at lunch on St Patrick’s day. When I heard Mojy joined GlobalFoundries I knew they were absolutely serious about the business side of semiconductor design and manufacturing.

Clearly the fabless model continues to thrive at 40nm and below. Due to the cost, only a handful of semiconductor manufacturers will develop 28nm process technology. Due to the cost, only the top fabless companies will design at 28nm, so the competition for their business will be fierce. The challenge for GlobalFoundries is to differentiate from Taiwan and that was the underlying message in this presentation: “GlobalFoundries is everything TSMC is not”.

Point #1 is the basis for their name, being global and not putting your semiconductor manufacturing eggs in one regional (Taiwan) basket. TSMC’s Morris Chang responded directly to this “Global Semiconductor Company” challenge by saying that TSMC will stay in Taiwan. The major reason being the economies of scale. According to Chang, TSMC only needs to run its Taiwan wafer fabrication plants at 40% capacity to break even, compared with 80% for “global” rivals.

The Chartered Semiconductor Common Platform marketing initiative will continue under GFI. In theory, the process development is collaborative and the cost is shared amongst the members. Common Platform clearly did not work for the now defunct Chartered Semiconductor which in my opinion was an implementation problem. If GFI drives this alliance hard it will work, believe it.

Point #2 is technology and the differing versions of HKMG technology. David Lammers did an excellent write-up: Gate First or Gate Last: Technologists Debate High-k . The bottom line is that Intel and TSMC will do Gate-Last. GFI, IBM, and other Common Platform Alliance members will do Gate-First. From what I have learned, Gate-Last will favor high performance and high yield designs but will require restricted design rules (RDRs). Gate-First will favor low power and smaller die sizes but may not scale past 22nm. I see this as a major battle ground for the foundry business. My opinion, whoever wins the 28nm node will lead the foundry business for the next decade.

Point #3 is semiconductor design enablement or the EDA, IP, and Design Services ecosystem. GlobalFoundries has Common Platform, TSMC has the Open Innovation Platform. One thing that has changed with Common Platform is that GFI is providing generous financial incentives for partners and we are talking about millions of dollars in life lines to companies that have struggled for profitability. GFI also pledged not to compete with partners, which is a direct shot at TSMC who has spent 100’s of millions of dollars developing proprietary design enablement technology.

Speaking of TSMC design enablement, the annual TSMC 2010 Technology Symposiums start next week in San Jose with Morris Chang as keynote speaker. TSMC has scheduled an in-person briefing for me with Shang Yi Chiang, senior vice president of R&D, to discuss 28nm technology so next week’s blog will be a follow-up to this.

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Redefining the Foundry Model: TSMC versus GlobalFoundries

Redefining the Foundry Model: TSMC versus GlobalFoundries
by Daniel Nenni on 04-10-2010 at 2:08 am
Categories: Foundries, GlobalFoundries, TSMC

The 17[SUP]th[/SUP] annual TSMC Technical Symposium finished its North American tour in Boston, a day before the Boston Marathon. I would like to be clever and say the foundry business is also a marathon but it clearly is not. If you watch TSMC, the foundry business is both a sprint AND a marathon!

In contrast to the previous blog on Global Foundries, the three key points to TSMC’s success are Leadership, Technology, and Experience. Rick Cassidy, President of TSMC North America, opened the symposiums with 30 slides of analogies and perspective featuring the US Olympic Bobsledding team.

Point #1 Leadership: Clearly TSMC is the leading foundry in all aspects of the business. The question is can TSMC continue in that role for another decade? I think the answer rests squarely on point #2.

Point #2 Technology: My 30 minute meeting with Dr. Shang-Yi Chiang, Vice President of TSMC R&D, should be a blog in itself but let me say here that he is one of the smartest, humble, and most believable men I have met. The big announcement Dr Chiang made was that TSMC would skip 22nm in favor of 20nm. My first question was why? Well, for two reasons (1) TSMC continues to see a 70% shrink as the optimum scaling factor: 40nm->28nm, 28nm->20nm, 20nm->14nm, 14nm-> 10nm. (2) Is my reason: Because TSMC can, and it gives them a competitive advantage. The predominate foundry business challenge is price cutting (2[SUP]nd[/SUP] and even 3[SUP]rd[/SUP] sourcing) so making your process as sticky as possible is the ultimate business goal. High volume designs will absolutely take advantage of the performance/power/area savings of a 20nm process versus 22nm. Look for the other foundries to follow suit as they did with 45 to 40nm in order to be competitive.

My second question for Dr Chiang was why Gate-Last versus Gate-First for 28nm? TSMC actually had parallel 28nm projects: Gate-First, Gate-Last, and Poly Gate. The winner was the Gate-Last 28nm implementation coupled with Restricted Design Rules due to scalability, performance, and yield. Dr Chang also stated that there is not an area penalty using RDRs which defies my personal experience with Recommend Design Rules.

My third question was about 40nm, what really happened with yield? Dr Chiang viewed it positively as a “learning” experience which resulted in technologies and practices that will enable 28nm and below (restricted design rules). TSMC saw 40nm designs with 4 billion + single VIAs, so VIA failure was an issue. Process variation was also a major issue, which I have blogged about before:

Moore’s Law and 28nm Yield
Moore’s Law and 40nm Yield


Dr Chaing did say that 40nm is “comfortably in production” at Fab 12 and 14. Expansion projects will double TSMC 40nm capacity by the end of the year. Giga Fabs like 12 and 14 can produce 100,000+ 12 inch wafers per month! Compared to Mini Fabs (10k+) and Mega Fabs (30k+). Capacity and the ability to satisfy the high volume needs of the top fabless semiconductor companies is key, believe it. He also said 28nm is on track with risk production in Q2 2010, which puts TSMC 6 months ahead of GlobalFoundries.

Point#3 Experience:TSMC also owns this one. IDM experience and Foundry experience are two very different things. One example is semiconductor IP and how it integrates into your design. Characterized, Modeled, Silicon proven IP from TSMC itself and TSMC early access partners like Virage Logic will ease integration issues and speed wafer sales. IP such as SRAM is used as pipe cleaners for new processes, which is why Virage was the first to announce products on TSMC 28nm. Other experience examples include silicon proven PDKs, Reference Design Kits and Flows.

This is my favorite Rick Cassidy slide, tight integration indeed:

My second favorite slide: mega fab costs are comparable to a Nimitz Class Aircraft carrier, minus the aircraft ($5B+). The question is, how many companies will be able to afford a fleet of aircraft carriers in the coming years, TSMC and?