In my submission about TSMC making some DFM analysis steps mandatory at 45nm (see “TSMC’s DFM Announcement”), I ended with a question about why the foundries can’t just write better design rules (and rule decks) to make sure all designs yield well. Here’s my take on this complicated question.
Continue reading “So, Why Not Just Write Better Rules?”
TSMC’s DFM Announcement
If you are a TSMC customer, no doubt you have heard TSMC is requiring lithography and planarity analysis for all 45nm designs. Their website says customers can either run it themselves, or contract TSMC services to do it. The most cost-effective way would be for the customers to run it themselves, but some might not have the resources to do that. Of course, by the time you pay TSMC to do it 3 or 4 times, you could have bought some tools and run it yourself. That’s good for Mentor and other EDA vendors, right? Probably, but there has to be more to it than that.
Continue reading “TSMC’s DFM Announcement”
So, Why Not Just Write Better Rules?
In my submission about TSMC making some DFM analysis steps mandatory at 45nm (see “TSMC’s DFM Announcement”), I ended with a question about why the foundries can’t just write better design rules (and rule decks) to make sure all designs yield well. Here’s my take on this complicated question.
Continue reading “So, Why Not Just Write Better Rules?”
TSMC’s DFM Announcement
If you are a TSMC customer, no doubt you have heard TSMC is requiring lithography and planarity analysis for all 45nm designs. Their website says customers can either run it themselves, or contract TSMC services to do it. The most cost-effective way would be for the customers to run it themselves, but some might not have the resources to do that. Of course, by the time you pay TSMC to do it 3 or 4 times, you could have bought some tools and run it yourself. That’s good for Mentor and other EDA vendors, right? Probably, but there has to be more to it than that.
Continue reading “TSMC’s DFM Announcement”
TSMC OIP Conference 2010 Critique!
Okay, this is more of a, “What I would do if I was TSMC” than a critique, but I needed a one word descriptor for the title. This was the third TSMC OIP Conference and I would guess about 250 people attended. This was the first time I have seen TSMC in “reactive” mode versus “proactive” leadership mode, so I was a bit disappointed. TSMC is THE industry leader and should NOT be looking in the rear view mirror at competitors that are barely visible.
The semiconductor landscape has dramatically changed during the contraction phase of the current business cycle. The strong got stronger by acquisition and aggressive business practices, and the rest of the fabless semiconductor companies either were: acquired, got smaller, or became IP companies. So TSMC, being a customer driven company, must also change strategies and the Open Innovation Platform IS the delivery system for that change.
The Pareto principle (also known as the 80-20 rule or the law of the vital few) states that, for many events, roughly 80% of the effects come from 20% of the causes. For semiconductors this is definitely the case. In fact, as a result of the recent economic chaos and consolidations I would guess that 90% of the silicon is shipped by 10% of the companies.
The foundry strategy for the top semiconductor companies is three-fold: Early Access, Capacity, and Wafer Pricing. TSMC is working hard on capacity and wafer pricing 24/7, believe it! There is no doubt in my mind that TSMC will continue to be the capacity and margin leader for 40nm, 28nm, and 20nm, which will keep the top foundry customers engaged. Early access however is a continuing challenge. For example, Design Rule Manuals (DRMS) are still in PDF format, 1,300+ pages long, and rapidly changing. Some of the rules are so complicated they are impossible to describe, and even harder to code and communicate, even within the foundry teams. This should be the focus of the TSMC OIP for the top semiconductor companies, a more automated and simplified information exchange, one that uses vendor neutral formats so customers cannot be held hostage by short sighted EDA vendors. The iPDK initiative is an excellent start but there is much more that can be accomplished.
For the other 90% of the semiconductor companies, the ones that cannot afford to develop custom design flows, PDK’s, and IP, the ones that cannot afford an in-house foundry team for early access, TSMC OIP is a critical enabler. Unfortunately, one of the messages of the conference was, “TSMC will not compete with partners”, which was a clear response to public relations pressure from the GlobalFoundries mantra, “We don’t compete with partners!”
Competition is what has made the semiconductor industry and semiconductors themselves what they are today! Competition is what drives innovation and keeps costs down. Not destructive competition, where the success of one depends on the failure of another, but constructive competition that promotes mutual survival and growth where everybody can win. The semiconductor design ecosystem is the poster child for destructive competition, which is why EDA ( SNPS, CDNS, MNTR, LAVA) valuations are a fraction of what they should be.
The TSMC Open Innovation Platform should be the cornerstone of the semiconductor design ecosystem. The ecosystem must NOT hold designers hostage with proprietary formats! The ecosystem MUSTinnovate to compete! The TSMC Open Innovation Platform MUST lead the way! TSMC is the #1 foundry and that will not change within my lifetime. TSMC must also be #1 in customer satisfaction and the design ecosystem ISwhere customer satisfaction begins.
TSMC GigaFab Tour!
During my most recent Taiwan trip I was not only afforded a meeting with Dr Mark Liu, Sr VP of TSMC, a guided tour of GigaFab #12 was also included. Even more impressive, I’m now considered “Elite” by Eva Airlines so I automatically get the good seats, better food, and VIP service. My wife, however, is not impressed with my Elite status so I still have to do chores around the house.
Mark Liu ramped up TSMC’s first 200mm fab in 1993 and has been building fabs for TSMC ever since. Mark’s favorite topic is the 300mm GigaFabs, Fab#12, Fab#14, and Fab #15 which TSMC just broke ground on last month. Clearly TSMC has learned a valuable lesson from the 40nm wafer shortage experience. Not having enough capacity is far more costly than having too much. After 40nm, customer priorities have certainly changed: Capacity is now the 1st concern with price a close 2[SUP]nd[/SUP], and last but not least design enablement. Please note that the perceived value of semiconductor design enablement is often overlooked but it is clearly the key enabler to TSMC’s expansive customer base.
After putting on the clean room space suit and being lightly air washed I entered a GigaFab for the first time and was literally speechless. If you know me personally, being speechless is not one of my strong suits so this was a new experience.
The insignias on the machines were logos and acronyms that I recognized but what struck me was the total automation of a GigaFab. Machines outnumbered man exponentially with 99% automation. Shuttles zoomed around on tracks above delivering thousands of 40nm wafers to the 300+ steps in the semiconductor manufacturing process. The few people I did see were at monitoring stations. Even more impressive than the billions of dollars of hardware in a GigaFab, is the millions of lines of software developed to run it: Automated Material Handling Systems (AMHS) for transporting, storing, and managing semiconductor wafer carriers and reticles plus Manufacturing Execution Systems (MES) software to manage overall production efficiency.
This year TSMC will spend a record $5.9B on capital expenditures. Approximately 75% will be used to expand TSMC’s 65/40/28nm technology capacity and 15% will be used for mainstream processes. The remainder will be used for equipment, R&D expenses, and new business such as solar and LED. TSMC’s newest Gigafab, Fab 15, will cost an estimated $9.4B. TSMC is also set to complete Phase 5 expansion at Fab 12, and Phase 4 expansion at Fab 14.
According to the most recent management report, TSMC has accelerated its capacity expansion plan for 2010. Total managed capacity was 2,749K 8-inch equivalent wafers in 2Q10, increased by 7% from 2,566K in 1Q10. Current capacity plan calls for an overall increase by 14% to 11,299 8- inch equivalent wafers, compared with 11,247 8-inch equivalent wafers planned in the last quarter.
Demand for TSMC’s advanced technology wafers in all major semiconductor market segments again increased quarter to quarter. Among the advanced technologies, 40nm not only increased an additional 2% of TSMC’s revenue share, the output of Gigafab wafers processed using 40nm technology increased by 30% sequentially.
The 40nm race is officially over, TSMC wins by a landslide in regards to capacity, price, and design enablement. The race for 28nm dominance however is still on between TSMC, Samsung, and GlobalFoundries. Samsung is in production at 32nm so moving to 28nm should just be a process shrink. For TSMC and GlobalFoundries, 28nm is a completely new node which will bring new technical challenges. Still, in my opinion, the foundry race to 28nm is too close to call today and it will certainly be an exciting finish!
Taiwan Semiconductor Manufacturing Corporation (NYSE: TSM)
After working with TSMC the past 10+ years the single most compelling question I have is why the stock (NYSE: TSM) is not at record highs. TSMC invented and continues to dominate the foundry business which is clearly the future of modern semiconductor design and manufacture. So why is this not a $20+ stock?!?!?
TSMC reports 36%+ net margins.
TSMC delivers a 24%+ return on equity.
TSMC just announced a 3.8% dividend.
TSMC carries $6B+ total cash.
TSMC has more capacity than its top rivals combined and a third Gigafab under construction.
TSMC has almost a 7X Market Cap margin between its closest rival UMC.
So why is TSM flatlining after yet another record setting month of sales?!?!?
One of my favorite stock crowdsourcing groups agrees that TSM is undervalued. Based on the aggregate intelligence of 165k+ investors participating in Motley Fool CAPS, TSMC has a 5 out of 5 star rating. A Motley Fool CAPS rating indicates a stock’s potential to outperform the S&P 500 as determined by the community. On CAPS, 99% of the 437 All-Star members who have rated Taiwan Semiconductor Manufacturing Corporation believe the stock will outperform the S&P 500 moving forward.
Just how strong is TSMC in the global semiconductor foundry business? Well, with 45%+ market share, TSMC is about three times as big as its closest competitor, #2 foundry UMC, and more than six times as big as the #4 China based foundry SMIC. Even with the overly documented 40nm yield ramping problems, TSMC is still in charge of that node with an estimated 80% market share. Today, the race for 28nm is on with production silicon due out in Q1 2011. TSMC? GlobalFoundries? Samsung? It’s a 3 horse race, expect a photo finish, the winner is the King of the Node!
TSMC is expected to finish 2010 at $12.5B.
TSMC serves the largest and most diverse customer base.
TSMC will spend a record $4.8B on capital expansion this year.
TSMC will be trying to recruit 5,000 new employees this year.
TSMC is investing heavily in LED and Solar thin film PV technologies.
TSMC is the favorite to win the 28nm node foundry race next year.
TSMC has a 5 star Motley Fool CAPS rating.
Out of control consumer spending will continue to drive foundry revenues to record highs. Semiconductor industry mystics see foundry revenue growing 30-40% in 2010 and 8-10% annually over the next 4 years. Meanwhile, in 2010 shares of TSM and UMC are down 12% and 21%, respectively. So tell me again why TSM is yet another under performing tech stock?!?!
TSMC Unveils First Ever AMS Reference Flow!
As a quick follow-up to my blog TSMC Extends Open Innovation Platform, TSMC today announced the Analog/Mixed Signal Reference Flow 1.0., another key collaborative component of TSMC’s Open Innovation Platform™.
The TSMC AMS Design Flow 1.0’s design package is integrated seamlessly on top of the 28nm interoperable process design kit (iPDK) and OpenAccess database and includes:
- Industry-first layout-dependent effect (LDE) aware design methodology
- TSMC-specific LDE engine
- Complete DFM-aware analog layout guideline and checker utility
- Advanced analog base cell (ABC) design
- Comprehensive design configuration management environment
- A robust front-end design and simulation platform for the analysis of design sensitivity, yield, multi process corners, noise effect, IR drop and electromigration (EM) issues.
- Constraint-driven analog placement and routing technology for fast layout prototyping, semi-automatic rule-driven layout assistance, and a demonstration of a PLL system design budgeting and loop filter layout synthesis capability.
- A Physical verification flow that includes accurate 3D field solver based extraction with intelligent RC reduction, and full DRC/LVS sign-off and dummy pattern insertion and extraction.
“TSMC’s Open Innovation Platformdeliverscomprehensive and innovative designtechnology services that remove advanced technology adoption barriers. Ithelpslower design costs andimprovestime-to-market,” said Dr Fu-Chieh Hsu, Vice President of Design Technology Platform and Deputy Head of Research & Development. “TheOpen Innovation Platform willnow beginaddressing system-level design’s cost and complexity and enable packaging of entire electronic systems onto multi-chip packages.”
The TSMC AMS Reference Flow 1.0 is developed and fully validated in collaboration with multiple EDA partners including:
- Apache Design Solutions
- Berkeley Design Automation
- Cadence
- Ciranova
- EdXact
- Mentor Graphics
- Magma Design Automation, Mentor
- Pyxis Technology
- Silicon Frontline
- SpringSoft
- Solido Design Automation
- Synopsys
“The design ecosystem must move beyond its current bounds and embrace the systems- level challenges that are at the heart of every design consideration. The Open Innovation Platformbegan setting the standard for ecosystem collaboration two years ago. TSMCcontinues to answer the market’s calland will build that same collaborative spirit on a system-level basis,” explained S.T. Juang, senior director, Design Infrastructure Marketing at TSMC.
TSMC Extends Open Innovation Platform
TSMC today extended one of the most effective semiconductor design enablement initiatives the semiconductor world has ever seen, the Open Innovation Platform (OIP). Morris Chang coined the term “OIP” himself in 2008, but the effort itself is 10+ years old with a collective cost > .5B$. My other blogs on topic include: TSMC OIP vs CDNS OIP Analysis, TSMC Open Innovation Platform Explained, andTSMC iPDK Debate.
The Open Innovation Platform’s global EcosystemAllianceprograms have grown to include 30 EDA partners, 38 IP partners, 23DesignCenterAlliance(DCA) partners, and 9 Value Chain Aggregator (VCA) partners. All partners participate in one or more of the Open Innovation Platform collaboration programs. TSMC also begins to work collaboratively with industry organizations, such as IPL Alliance and Si2, to promote the interoperability standards based on TSMC interoperable EDA formats.
Impressive! But is TSMC the #1 semiconductor foundry because of their design enablement activities? Or is this design enablement initiative #1 because TSMC is the industry leading foundry?
I like the executive quotes included in the official TSMC press release, they speak volumes:
“The electronic design community is embracing the EDA360 vision to enable fastest approach from concept to consumer and together with IP suppliers, EDA vendors and silicon manufacturers, we have diligently collaborated to build a cohesive path for designers,” said Lip-Bu Tan, president and chief executive officer, Cadence. “TSMC’s Open Innovation Platform is a proven, integral part of this path. TSMC’s Open Innovation Platform will now make significant advancements in low-power, mixed-signal, system-level and 3D-IC design to enable further productivity improvements that our mutual customers need.”
News flash: The semiconductor community has NOT embraced EDA360. Just because you keep saying something over and over does not make it true, especially when it is self serving. I have spoken to dozens of semiconductor industry professionals and the foregone conclusion is that EDA360 is aNothing Burger!
“Going forward,Mentor and TSMC are developing complete solutions for the TSMC design ecosystem, ” said Walden C. Rhines, Chairman and CEO,Mentor Graphics. “The TSMC OIP effort is not just words — theMentor Track in Reference Flow 11.0, and the co-developed iDRC and iLVS languages, are real usable results.”
I like Wally’s style here, say more with less. My lunch with Wally is next week so hopefully I can get him to say more on the subject.
“Collaboration across the entire design eco-system — customers, foundries, IP and EDA suppliers — is critical for lower design risk and cost, better power and performance, and customer differentiation, ” said Aart de Geus, Chairman and CEO, Synopsys. “The new technologies in this phase of TSMC OIP, such as system-level design, analog/mixed-signal (AMS) design and thru-silicon-via, bring key solutions to speed System-to-IC realization.”
Aart is pointing out that the TSMC OIP not only competes directly with the Cadence EDA360 OIP, it plays to the strengths of Synopsys. In fact, the EDA360 Manifesto highlights the strengths of both Mentor and Synopsys: System Realization, SoC Realization, and Silicon Realization. Synopsys and Mentor own EDA360.
The most interesting quote, or lack there of, is from Magma CEO Rajeev Madhaven. Seriously, Magma is an integral part of the TSMC OIP expansion but no quote from Rajeev? I would like to think it is a conspiracy against Magma by the top 3 EDA CEO’s as a result of Magma’s business practices, but I’m sure there is a far less interesting explanation.
TSMC versus GlobalFoundries: Semiconductor Design Enablement!
As mentioned in previous blogs, design enablement is a key enabler to fabless semiconductor design and manufacture, without question. The purpose of this blog (in 500 words) is to compare and contrast two very different design enablement strategies and engage the semiconductor community in a meaningful discussion.
The GlobalFoundry strategy is straight forward so let’s start there. GFI is partnering with leading design enablement companies to advance semiconductor design at the 28nm node. GFI is committed to becoming the FIRST SOURCE for 28nm, competing directly with TSMC, while other foundries have in the past offered “T” like processes for 2[SUP]nd[/SUP] and 3[SUP]rd[/SUP] source manufacturing strategies (UMC, Chartered Semi, SMIC).
GFI is taking the sniper approach to partnerships rather than the traditional foundry business model of working with everybody (EDA, Semi IP, and Fabless ASIC companies). GFI has stated very clearly that they will not compete with partners and will in fact invest financially in the design enablement industry by purchasing products and services from said partners.
On the EDA side it is Synopsys for digital design, Cadence for AMS design, and Mentor for Verification and DFM. IP is ARM, Synopsys, Virage, and a collection of smaller companies. ASIC services is eSilicon, Open-Silicon, and SOCLE. Mask services is DNP, Hoya, and Tappan. I have heard that GFI has already cut millions of dollars of purchase orders with EDA and Semi IP companies. It would not surprise me at all if GFI is now the #1 customer of said partners so look for more GFI specific EDA tools, IP, and services in the coming quarters.
ARM, IBM, Samsung, GLOBALFOUNDRIES and Synopsys Announce Delivery of 32/28nm HKMG Vertically Optimized Design Platform
TSMC on the other hand has, over the last 10 years, implemented the shotgun approach to partnerships (TSMC Open Innovation Platform) which includes a “co-opetition” clause. Shotgun approach means TSMC works with EDA companies big and small, qualifying dozens of EDA tools and hundreds of silicon proven IP. Co-opetition means cooperative competition with partners via TSMC’s internal: IP development, mask services, and ASIC design services (Global Unichip Corp).
Two very different strategies, two very different outcomes?
Will GFI succeed in getting the 28nm 1[SUP]st[/SUP] source business? If 80% of foundry silicon is shipped by the top 20 fabless semiconductor companies is that your target market? Those top 20 companies are experts in semiconductor design enablement and do not need help with off the shelf tools and IP, what value can GFI really add there? And what about the 80% of the companies that ship 20% of the silicon? Can they really be ignored when one of them could easily be the next Cisco or Broadcom? What do you think?
Will TSMC invest more in the design enablement industry and compete less with partners? Can TSMC continue to take on all customers, big profit margin and small? TSMC has spent 100’s of millions of dollars on Semi IP, PDKs, and reference flows. Can that amount of spending continue to be justified? How do you think this will play out?
Answers to these questions will hopefully come in the form of comments so please share your opinions. The foundries and thousands of other people read my blog so lets hear it. In fact, more people read my blog than attended #47DAC!
Next week’s blog “TSMC versus GlobalFoundries: Semiconductor Design Enablement! II” will focus on feedback from TSMC and GFI executives. See you on Monday!