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TSMC vs GlobalFoundries IBM Samsung

TSMC vs GlobalFoundries IBM Samsung
by Daniel Nenni on 12-05-2010 at 9:52 pm
Categories: Foundries, GlobalFoundries, TSMC


GlobalFoundries has brought the Common Platform Alliance back from the dead!?!?!?! Good thing too as it is probably their most comprehensive weapon against TSMC and answers the single biggest question customers have at 28nm and that is; Will there be enough CAPACITY?

The Common Platform technology alliance hosted its first-ever Technology Forum on Tuesday, November 6, 2007 at the Santa Clara Convention center. I was there, the food was pretty good. No airline box lunch, this was a regular three course sit down meal.
The mission statement back then was:

IBM, Chartered and Samsung Electronics have broken new ground in the semiconductor industry with a unique collaboration focused on leading-edge, jointly developed digital CMOS process technologies and advanced manufacturing. The Common Platform model is further supported by a comprehensive ecosystem of design enablement and implementation partners from the EDA, IP and design services industries. This ecosystem allows foundry customers to source their chip designs to multiple 300mm foundries with minimal design work, unprecedented flexibility and choice. The Common Platform model features 90nm, 65nm, 45nm and 32nm technologies.

Unfortunately it did NOT quite happen that way. The ONLY reason why fabless semiconductor companies were able to manufacture the same design in second (UMC), third (Chartered Semiconductor), and fourth (SMIC) source fabs at 130nm, 90nm, 65nm, and 40nm is because they all were “compatible” with TSMC. Artisan Components (ARM) enabled this wave of multisourcing by porting the physical IP they developed for TSMC to the other fabs.

Here is the Common Platform mission statement for 2011:

IBM, Samsung and GLOBALFOUNDRIES are members of the Common Platform alliance focusing on leading-edge, jointly developed digital CMOS process technologies and advanced manufacturing. The Common Platform model is further supported by a comprehensive ecosystem of design enablement and implementation partners from the EDA, IP and design services industries. This ecosystem allows foundry customers to source their chip designs to multiple 300mm foundries with minimal design work, unprecedented flexibility and choice.

If in fact Common Platform can enable this 2[SUP]nd[/SUP] and 3[SUP]rd[/SUP] sourcing at 28nm and below it will give the top fabless semiconductor companies the perceived capacity they need to be successful. Samsung is the capacity wild card here and is really the only company strong enough in capitol ANDtechnology to challenge TSMC, so this is a big fat hairy deal.

You can register for the Common Platform Technology Forum here. I would register quickly as the 2,000 seats will sell out well before the doors open. Here is the formal invite:

Tomorrow’s Technology – Delivered Today
The Common Platform Alliance of IBM, Samsung and GLOBALFOUNDRIES invites you join us at our technology forum on Tuesday, January 18. This free, daylong event will feature the Common Platform’s innovative collaboration to deliver industry-leading technology that breaks new ground in performance and power efficiency for the 32/28nm technology nodes and beyond.
The technology forum features keynotes from industry leaders and presentations from senior members of the Common Platform partners. Topics include:

  • Technical advancements of the innovative 32/28nm low-power high-k metal gate (HKMG) process technology optimized for the next generation of communications and smart mobile devices
  • Technology innovations in SoC enablement solutions, materials science, process technology and manufacturing
  • Proven design and manufacturing solutions from the alliance and its ecosystem partners
  • The invention process and technology roadmap to 20nm and beyond

A key part of the forum will focus on collaboration for technology delivery, highlighting the rich and broad ecosystem of design enablement and implementation partners through a Partner Pavilion featuring leading EDA, IP, library, mask, back-end and design services companies.
Mark your calendar for this complementary one-day technical event!
This is a special advance invitation. Please register early as seating is limited.

Common Platform Alliance
www.commonplatform.com

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TSMC Versus Intel?

TSMC Versus Intel?
by Daniel Nenni on 11-07-2010 at 7:18 pm
Categories: Foundries, TSMC


The big announcement last week was Intel opening up its 22nm manufacturing facilities to an outside company. Even better it’s an FPGA company. There are literally hundreds of write ups on this landmark event so it is definitely blog worthy. But what does it really mean? I have read (5) possibilities:

(1) Intel enters the FPGA business
(2) Intel enters the foundry business
(3) Intel ramps advanced processes with FPGA technology
(4) Intel adds FPGA muscle to Atom
(5) Intel wants Achronix asynchronous logic IP

EETimes actually did a nice write-up here, so I will skip the press release stuff and get right to my personal experience and expert opinion:

Intel entering the FPGA business (again)?Starting from zero (Achronix) in a highly competitive market that relies on a multi tiered sales channel, silicon proven IP, and free design software? I don’t think so. I worked for an FPGA start-up (Gatefield, bought by Atcel) and can tell you, competing against Altera/Xilinx is your worst nightmare. These people are design win commandos and will stop at nothing to win a socket. GateField had a 2x density advantage and was also an ASIC replacement (used standard design tools) but didn’t have a chance against the FPGA cartels. Neither did Actel and the dozen other FPGA start-ups that have since failed. After spending 2 years searching Northern California for design starts with ARC, eSilicon, and Virage, after identifying 500+ companies and profiling their application and design ecosystem, I did not find a single Achronix Speedster 22i customer. And just so you know, eSillicon did the silicon implementation of the flagship TSMC 65nm version of Speedster not Achronix.

Intel entering the foundry business? This would be more of an “Intel Versus Samsung” thing since both are pure-play semiconductor foundry posers. Intel has been dabbling in the foundry/ASIC business for years so this is not big news. Today, Intel is run by bean counters who would be best advised to focus on the high margin microprocessor business before ARM bakes their beans. Android is ARM based and between Android phones and tablets the PC/laptop business faces extinction! Now if Intel offered special foundry services for Atom based designs that would be interesting.

Intel ramps advanced processes with FPGA technology? This is entirely possible but certainly not a big enough gain to justify the risk/expense. TSMC uses Altera to ramp processes, FPGA companies are always first to a node and the repetitive structures they use work well for this. SRAM is used for the same purpose which is one of the reasons why the IP guys see new processes up close and personal.

Intel adds FPGA muscle to Atom? Not likely. ARM is partners with Altera and Xilinx so Intel should do the same. Installed base of customers means everything for this strategy to work.

Intel wants Achronix asynchronous logic IP. This is believable. An FPGA friend of mine explained this to me and it made complete sense. Unfortunately it was very long winded and uber technical (this guy is from UC Berkley) so I could never do it justice, so I will leave it at that.

But this is all just false paths to throw the mainstream media off the track. The REAL reason Intel made this announcement:

A CHEAP SHOT AT AMD / GLOBALFOUNDRIES!

Intel is clearly feeling the heat from AMD, especially with the integrated CPU/GPU Llano chip coming out of the GlobalFoundries Dresden fab. Llano, the world’s first quad-core microprocessor with integrated DirectX 11 graphics processor, is made using 32nm silicon-on-insulator process technology with high-K metal gate (HKMG). Llano competes with Intel Corp’s much anticipated Sandy Bridge integrated microprocessor. Intel can be petty at times and this is one of those times, believe it!

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Semiconductor Forecast: 2010 Boom – 2011 Bust?

Semiconductor Forecast: 2010 Boom – 2011 Bust?
by Daniel Nenni on 10-15-2010 at 6:34 pm
Categories: Foundries, TSMC


Again, my economic bellwether is TSMC, and judging by the first half, 2010 will go down as one of the most profitable years the semiconductor industry has ever seen. In the 2[SUP]nd[/SUP] quarter the foundries again posted record breaking wafer shipments, revenues, and profits. 3[SUP]rd[/SUP] quarter foundry financials should be even stronger. Bottom line, the semiconductor industry will see its largest yearly expansion and will easily break the $300B barrier in 2010.
Pent up demand certainly explains the V recovery. My family was in financial lock down in 2009 but will more than make up the difference in 2010. New laptops, mobile phones, we even added a car and new energy efficient kitchen appliances, all semiconductor laden devices.

Unfortunately, TSMC CEO Morris Chang recently commented that “inventory levels of its fabless and IDM customers have increased at a rate close to the increase in sales.” Total semiconductor inventories did grow 10% in Q2 which is double what was forecasted. Customers of both TSMC and UMC reported high inventory sequential growth levels for the second quarter of 2010:

  • Qualcomm’s grew 11%
  • Broadcom’s went up by 21.6%
  • MediaTek’s jumped 24%
  • AMD’s rose 14%
  • TI’s climbed 10%


An August 5th post by Bill Jewel of Semiconductor Intelligence summarizes recent growth forecasts by the top analysts, which have risen dramatically month-to-month throughout 2010. Seriously, forecasting semiconductor growth this year has been like forecasting the weather, anything farther than 10 days out is just not reliable!

Bill however does not exactly follow my semiconductor Boom to Bust prediction in 2011:
Electronics new orders and production data from key countries also indicate a strong recovery.U.S.electronics new orders were up 14% in 2[SUP]nd[/SUP] quarter 2010 after showing a year-to-year decline of 14% in 2[SUP]nd[/SUP] quarter 2009. The European Union, Japan and Taiwan all had significant declines in electronics in early 2009, but have all bounced back to solid growth in 2010. China electronics production was the least affected by the recession, with 1[SUP]st[/SUP] quarter 2009 flat with a year ago. Chinahas recovered back to double-digit growth since 4[SUP]th[/SUP] quarter 2009.

Nor does Bill support my position on growing semiconductor inventories:

What about electronics inventories? Are they getting ahead of demand? Data from theU.S.andJapanshow the ratio of the inventory held by electronics manufacturers to their shipments began to climb in early 2008. The ratio peaked inJapanin December 2008 and then declined rapidly. In 2010, the ratio inJapanhas leveled off in the 80% to 90% range, below where it was in early 2008. TheU.S.ratio peaked in March 2009 and has declined to the 130% to 140% range, about the same level as the beginning of 2008.

Unfortunately, government stimulus packages are expiring and leading economic indicators: consumer confidence index (CCI), jobs, housing, etc… are in decline, which supports my 2011 semiconductor bust (back to single digit growth) prediction. Not that there is anything wrong that!
Hopefully the recent semiconductor foundry CAPEX surge will result in excess manufacturing capacity in 2012, which will in turn keep chip prices low. Remember, a modern GigaFab only has to run at 40% capacity to break even. Low chip prices will then support rampant consumerism and we will back to double digit semiconductor growth yet again. That’s my story and I’m sticking to it!

lang: en_US

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What Do You Mean by Mandatory?

What Do You Mean by Mandatory?
by glforte on 10-14-2010 at 6:00 pm
Categories: EDA, Foundries, Siemens EDA, TSMC

When TSMC and Mentor Graphics held a joint seminar for mutual customers to go over new DFM requirements at 45/40 nm, two customers basically asked the same question, “What do you mean by mandatory?” Of course, TSMC wasn’t going to stand over them and say, “Mandatory means mandatory, what part of mandatory don’t you understand?” :=) TSMC admitted that they hadn’t yet changed the tape-out checklist to forcibly include the DFM checks (CMP and LPC). This is what begs the question, what do you mean by mandatory?
Continue reading “What Do You Mean by Mandatory?”

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What Do You Mean by Mandatory?

What Do You Mean by Mandatory?
by glforte on 10-14-2010 at 6:00 pm
Categories: EDA, Foundries, Siemens EDA, TSMC

When TSMC and Mentor Graphics held a joint seminar for mutual customers to go over new DFM requirements at 45/40 nm, two customers basically asked the same question, “What do you mean by mandatory?” Of course, TSMC wasn’t going to stand over them and say, “Mandatory means mandatory, what part of mandatory don’t you understand?” :=) TSMC admitted that they hadn’t yet changed the tape-out checklist to forcibly include the DFM checks (CMP and LPC). This is what begs the question, what do you mean by mandatory?
Continue reading “What Do You Mean by Mandatory?”

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So, Why Not Just Write Better Rules?

So, Why Not Just Write Better Rules?
by glforte on 10-14-2010 at 4:00 pm
Categories: EDA, Foundries, Siemens EDA, TSMC

In my submission about TSMC making some DFM analysis steps mandatory at 45nm (see “TSMC’s DFM Announcement”), I ended with a question about why the foundries can’t just write better design rules (and rule decks) to make sure all designs yield well. Here’s my take on this complicated question.
Continue reading “So, Why Not Just Write Better Rules?”

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TSMC’s DFM Announcement

TSMC’s DFM Announcement
by glforte on 10-14-2010 at 4:00 pm
Categories: EDA, Foundries, Siemens EDA, TSMC

If you are a TSMC customer, no doubt you have heard TSMC is requiring lithography and planarity analysis for all 45nm designs. Their website says customers can either run it themselves, or contract TSMC services to do it. The most cost-effective way would be for the customers to run it themselves, but some might not have the resources to do that. Of course, by the time you pay TSMC to do it 3 or 4 times, you could have bought some tools and run it yourself. That’s good for Mentor and other EDA vendors, right? Probably, but there has to be more to it than that.
Continue reading “TSMC’s DFM Announcement”

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So, Why Not Just Write Better Rules?

So, Why Not Just Write Better Rules?
by glforte on 10-14-2010 at 4:00 pm
Categories: EDA, Foundries, Siemens EDA, TSMC

In my submission about TSMC making some DFM analysis steps mandatory at 45nm (see “TSMC’s DFM Announcement”), I ended with a question about why the foundries can’t just write better design rules (and rule decks) to make sure all designs yield well. Here’s my take on this complicated question.
Continue reading “So, Why Not Just Write Better Rules?”

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TSMC’s DFM Announcement

TSMC’s DFM Announcement
by glforte on 10-14-2010 at 4:00 pm
Categories: EDA, Foundries, Siemens EDA, TSMC

If you are a TSMC customer, no doubt you have heard TSMC is requiring lithography and planarity analysis for all 45nm designs. Their website says customers can either run it themselves, or contract TSMC services to do it. The most cost-effective way would be for the customers to run it themselves, but some might not have the resources to do that. Of course, by the time you pay TSMC to do it 3 or 4 times, you could have bought some tools and run it yourself. That’s good for Mentor and other EDA vendors, right? Probably, but there has to be more to it than that.
Continue reading “TSMC’s DFM Announcement”

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TSMC OIP Conference 2010 Critique!

TSMC OIP Conference 2010 Critique!
by Daniel Nenni on 10-10-2010 at 10:18 pm
Categories: EDA, Foundries, TSMC

Okay, this is more of a, “What I would do if I was TSMC” than a critique, but I needed a one word descriptor for the title. This was the third TSMC OIP Conference and I would guess about 250 people attended. This was the first time I have seen TSMC in “reactive” mode versus “proactive” leadership mode, so I was a bit disappointed. TSMC is THE industry leader and should NOT be looking in the rear view mirror at competitors that are barely visible.

The semiconductor landscape has dramatically changed during the contraction phase of the current business cycle. The strong got stronger by acquisition and aggressive business practices, and the rest of the fabless semiconductor companies either were: acquired, got smaller, or became IP companies. So TSMC, being a customer driven company, must also change strategies and the Open Innovation Platform IS the delivery system for that change.

The Pareto principle (also known as the 80-20 rule or the law of the vital few) states that, for many events, roughly 80% of the effects come from 20% of the causes. For semiconductors this is definitely the case. In fact, as a result of the recent economic chaos and consolidations I would guess that 90% of the silicon is shipped by 10% of the companies.

The foundry strategy for the top semiconductor companies is three-fold: Early Access, Capacity, and Wafer Pricing. TSMC is working hard on capacity and wafer pricing 24/7, believe it! There is no doubt in my mind that TSMC will continue to be the capacity and margin leader for 40nm, 28nm, and 20nm, which will keep the top foundry customers engaged. Early access however is a continuing challenge. For example, Design Rule Manuals (DRMS) are still in PDF format, 1,300+ pages long, and rapidly changing. Some of the rules are so complicated they are impossible to describe, and even harder to code and communicate, even within the foundry teams. This should be the focus of the TSMC OIP for the top semiconductor companies, a more automated and simplified information exchange, one that uses vendor neutral formats so customers cannot be held hostage by short sighted EDA vendors. The iPDK initiative is an excellent start but there is much more that can be accomplished.

For the other 90% of the semiconductor companies, the ones that cannot afford to develop custom design flows, PDK’s, and IP, the ones that cannot afford an in-house foundry team for early access, TSMC OIP is a critical enabler. Unfortunately, one of the messages of the conference was, “TSMC will not compete with partners”, which was a clear response to public relations pressure from the GlobalFoundries mantra, “We don’t compete with partners!”

Competition is what has made the semiconductor industry and semiconductors themselves what they are today! Competition is what drives innovation and keeps costs down. Not destructive competition, where the success of one depends on the failure of another, but constructive competition that promotes mutual survival and growth where everybody can win. The semiconductor design ecosystem is the poster child for destructive competition, which is why EDA ( SNPS, CDNS, MNTR, LAVA) valuations are a fraction of what they should be.

The TSMC Open Innovation Platform should be the cornerstone of the semiconductor design ecosystem. The ecosystem must NOT hold designers hostage with proprietary formats! The ecosystem MUSTinnovate to compete! The TSMC Open Innovation Platform MUST lead the way! TSMC is the #1 foundry and that will not change within my lifetime. TSMC must also be #1 in customer satisfaction and the design ecosystem ISwhere customer satisfaction begins.