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TSMC Versus The FabClub!

TSMC Versus The FabClub!
by Daniel Nenni on 01-23-2011 at 11:00 pm
Categories: Foundries, TSMC


The Common Platform Technology Forum last week was not well attended, less than half than the GlobalFoundries Conference. It was deja vu of previous CP forums but there were a couple of surprises to go with the disappointment. The lunch line was long, but fortunately I was escorted to the press lunch featuring VIP’s from Samsung, IBM and GlobalFoundries. Yes, I still blog for food.

While I originally thought bringing back Common Platform from the dead was a good idea, attending the Forum definitely changed my mind. According to the presentations, Common Platform WAS wildly successful, but clearly it was not. Chartered Semiconductor WAS Common Platform and Chartered WAS purchased by GlobalFoundries for pennies on the total investment dollar, right?

I would have rather them said, “Look, Common Platform has changed and this is why it WILL be successful from this day forward”. A little humility goes a long way, it also shows respect for the intelligence of the audience. My opinion now is that Common Platform should be laid to rest, dead is dead, no coming back. Only Zombies come back from the dead and no one wants a Common Zombie Platform.

The surprises were twofold:

(1) The FabClub will move to Gate-Last technology for 20nm and beyond. This is HUGE! Gate-Last and Gate-First refer to the point at which a metal gate electrode is dropped onto the wafer, before or after the high-temperature heating process. I spoke with Dr. Shang-Yi Chiang, Vice President of TSMC R&D, and asked why Gate-Last versus Gate-First for 28nm? TSMC actually had parallel 28nm projects: Gate-First, Gate-Last, and Poly-Gate. The winner was the Gate-Last 28nm implementation coupled with Restricted Design Rules (RDRs) due to scalability, performance, and yield. Dr Chang also stated that there is no density penalty using RDRs. When GFI starts yielding we will know for sure which implementation is best at 28nm but it looks like Shang-Yi was right. TSMC has 28nm Silicon with Altera, Nvidia, Xilinx, and AMD/ATI. The only silicon announced from GFI is ARM test chips.

(2) The FabClub fabs (IBM, GFI, Samsung) are GDSII compatible but not mask compatible. This may be ignorance on my part, but I assumed you could move designs across foundries without millions of dollars in mask and other costs. GDS II compatible means design rule compatible, they can use the same DRC decks.

The underlying theme I got from the forum was cost (yawn). The cost of future semiconductor research, development, and manufacturing will be too much for one foundry (TSMC) and will require a FabClub. Even if it was true it’s boring. An even better forum theme, one which I personally endorsed, would have been:

“Common Platform is bringing the collaborative IDM semiconductor design and manufacturing culture to the merchant foundry business!” Daniel Nenni

Samsung, IBM, and AMD are born and bred IDMs, GFI is a foundry. Take the best of both worlds and deliver. It’s a winner, believe it. A distinct advantage GlobalFoundries has over the competition and FabClub partners is communication. These guys have raised the bar! My advice is for IBM and Samsung to step aside and let GlobalFoundries lead the way.

I’m in Taiwan, this week is the TSMC fiscal year end conference call with Morris Chang. Expect really good news: 12″ fabs are full, TSMC will hire more than 6,500 new employees in 2011, TSMC increased R&D expenses 50% and set an $8 billion+ CAPEX. Very big numbers considering semiconductor analysts are fortunetelling single digit semiconductor industry growth in 2011! FOOLS!

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The Future of Semiconductor Design!

The Future of Semiconductor Design!
by Daniel Nenni on 12-26-2010 at 10:15 pm
Categories: EDA, Foundries, TSMC

Is EDA still an appropriate term for what we do? What applications will drive future semiconductor design innovation? Will further consolidation be required for EDA to thrive again? They are all good questions, questions that will hopefully be properly addressed at the EDAC CEO Forecast and Industry Vision event next week but here are my thoughts:

Is EDA still an appropriate term for what we do? According to the most recent press releases:
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced……

Cadence Design Systems, Inc. (NASDAQ: CDNS), a global leader in electronic design innovation….

Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions………
Magma® Design Automation Inc. (Nasdaq:LAVA), a provider of chip design software…..

Not that EDA companies ever called themselves EDA companies in print, but I do see a disconnect here. One of the things I do for a living is provide background information to semiconductor industry investors. The foundries and their top customers are of BIG INTEREST, EDA and IP not so much. I have even conference called with analysts who have JUST attended EDA CEO presentations and they still don’t see the value in EDA. If you want to know the number one problem with EDA, that is it, communication. We really suck at it.

What applications will drive future semiconductor design? That should be obvious after Christmas, EMBEDDED SYSTEMS! We got a new minivan for Christmas and you would not believe the electronics packages that are available today. Seriously, it’s like piloting a space shuttle. There has to be dozens of microprocessors and sensors embedded into this vehicle. Video cameras, collision avoidance, satellite, GPS, split screen DVD, electric doors, and disappearing seats just to name a few. Seriously, you push a button and the back seat automatically folds into the floor. The manual for this vehicle is hundreds of pages, hopefully one of my kids will read it someday.

Currently embedded systems account for $200B+ of the $300B+ semiconductor revenues. That is if we can agree that an “embedded system” is an electronic device with a special purpose processor, including smartphones. The other $100B+ has general purpose processors driving them. Future semiconductor growth will come from the embedded side for sure.

Will further consolidation be required for EDA to thrive again?Yes of course, I think we can all agree on that. My biggest concern however is the lack of EDA and IP start-ups. You will be hard pressed to find investors for semiconductor design. The top EDA companies are not helping much either. Remember when EDA partner programs were open? How about when the top EDA companies had incubators and VC funds? If the top EDA companies spent half as much time nurturing emerging companies as they do trying to kill them we would all be better off.

Here’s the irony on the investment side, VC’s are spending billions of dollars on Facebook, Twitter, Zynga, and other mindless applications, but when it comes to the tools and IP that build the platforms? Pffft. How about when Google, Apple, and/or Oracle start buying ARM, Synopsys, and the other key semiconductor enablers? That will shake things up a bit and maybe we will remember where we all came from, START-UPS!

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TSMC vs GlobalFoundries IBM Samsung

TSMC vs GlobalFoundries IBM Samsung
by Daniel Nenni on 12-05-2010 at 9:52 pm
Categories: Foundries, GlobalFoundries, TSMC


GlobalFoundries has brought the Common Platform Alliance back from the dead!?!?!?! Good thing too as it is probably their most comprehensive weapon against TSMC and answers the single biggest question customers have at 28nm and that is; Will there be enough CAPACITY?

The Common Platform technology alliance hosted its first-ever Technology Forum on Tuesday, November 6, 2007 at the Santa Clara Convention center. I was there, the food was pretty good. No airline box lunch, this was a regular three course sit down meal.
The mission statement back then was:

IBM, Chartered and Samsung Electronics have broken new ground in the semiconductor industry with a unique collaboration focused on leading-edge, jointly developed digital CMOS process technologies and advanced manufacturing. The Common Platform model is further supported by a comprehensive ecosystem of design enablement and implementation partners from the EDA, IP and design services industries. This ecosystem allows foundry customers to source their chip designs to multiple 300mm foundries with minimal design work, unprecedented flexibility and choice. The Common Platform model features 90nm, 65nm, 45nm and 32nm technologies.

Unfortunately it did NOT quite happen that way. The ONLY reason why fabless semiconductor companies were able to manufacture the same design in second (UMC), third (Chartered Semiconductor), and fourth (SMIC) source fabs at 130nm, 90nm, 65nm, and 40nm is because they all were “compatible” with TSMC. Artisan Components (ARM) enabled this wave of multisourcing by porting the physical IP they developed for TSMC to the other fabs.

Here is the Common Platform mission statement for 2011:

IBM, Samsung and GLOBALFOUNDRIES are members of the Common Platform alliance focusing on leading-edge, jointly developed digital CMOS process technologies and advanced manufacturing. The Common Platform model is further supported by a comprehensive ecosystem of design enablement and implementation partners from the EDA, IP and design services industries. This ecosystem allows foundry customers to source their chip designs to multiple 300mm foundries with minimal design work, unprecedented flexibility and choice.

If in fact Common Platform can enable this 2[SUP]nd[/SUP] and 3[SUP]rd[/SUP] sourcing at 28nm and below it will give the top fabless semiconductor companies the perceived capacity they need to be successful. Samsung is the capacity wild card here and is really the only company strong enough in capitol ANDtechnology to challenge TSMC, so this is a big fat hairy deal.

You can register for the Common Platform Technology Forum here. I would register quickly as the 2,000 seats will sell out well before the doors open. Here is the formal invite:

Tomorrow’s Technology – Delivered Today
The Common Platform Alliance of IBM, Samsung and GLOBALFOUNDRIES invites you join us at our technology forum on Tuesday, January 18. This free, daylong event will feature the Common Platform’s innovative collaboration to deliver industry-leading technology that breaks new ground in performance and power efficiency for the 32/28nm technology nodes and beyond.
The technology forum features keynotes from industry leaders and presentations from senior members of the Common Platform partners. Topics include:

  • Technical advancements of the innovative 32/28nm low-power high-k metal gate (HKMG) process technology optimized for the next generation of communications and smart mobile devices
  • Technology innovations in SoC enablement solutions, materials science, process technology and manufacturing
  • Proven design and manufacturing solutions from the alliance and its ecosystem partners
  • The invention process and technology roadmap to 20nm and beyond

A key part of the forum will focus on collaboration for technology delivery, highlighting the rich and broad ecosystem of design enablement and implementation partners through a Partner Pavilion featuring leading EDA, IP, library, mask, back-end and design services companies.
Mark your calendar for this complementary one-day technical event!
This is a special advance invitation. Please register early as seating is limited.

Common Platform Alliance
www.commonplatform.com

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TSMC Versus Intel?

TSMC Versus Intel?
by Daniel Nenni on 11-07-2010 at 7:18 pm
Categories: Foundries, TSMC


The big announcement last week was Intel opening up its 22nm manufacturing facilities to an outside company. Even better it’s an FPGA company. There are literally hundreds of write ups on this landmark event so it is definitely blog worthy. But what does it really mean? I have read (5) possibilities:

(1) Intel enters the FPGA business
(2) Intel enters the foundry business
(3) Intel ramps advanced processes with FPGA technology
(4) Intel adds FPGA muscle to Atom
(5) Intel wants Achronix asynchronous logic IP

EETimes actually did a nice write-up here, so I will skip the press release stuff and get right to my personal experience and expert opinion:

Intel entering the FPGA business (again)?Starting from zero (Achronix) in a highly competitive market that relies on a multi tiered sales channel, silicon proven IP, and free design software? I don’t think so. I worked for an FPGA start-up (Gatefield, bought by Atcel) and can tell you, competing against Altera/Xilinx is your worst nightmare. These people are design win commandos and will stop at nothing to win a socket. GateField had a 2x density advantage and was also an ASIC replacement (used standard design tools) but didn’t have a chance against the FPGA cartels. Neither did Actel and the dozen other FPGA start-ups that have since failed. After spending 2 years searching Northern California for design starts with ARC, eSilicon, and Virage, after identifying 500+ companies and profiling their application and design ecosystem, I did not find a single Achronix Speedster 22i customer. And just so you know, eSillicon did the silicon implementation of the flagship TSMC 65nm version of Speedster not Achronix.

Intel entering the foundry business? This would be more of an “Intel Versus Samsung” thing since both are pure-play semiconductor foundry posers. Intel has been dabbling in the foundry/ASIC business for years so this is not big news. Today, Intel is run by bean counters who would be best advised to focus on the high margin microprocessor business before ARM bakes their beans. Android is ARM based and between Android phones and tablets the PC/laptop business faces extinction! Now if Intel offered special foundry services for Atom based designs that would be interesting.

Intel ramps advanced processes with FPGA technology? This is entirely possible but certainly not a big enough gain to justify the risk/expense. TSMC uses Altera to ramp processes, FPGA companies are always first to a node and the repetitive structures they use work well for this. SRAM is used for the same purpose which is one of the reasons why the IP guys see new processes up close and personal.

Intel adds FPGA muscle to Atom? Not likely. ARM is partners with Altera and Xilinx so Intel should do the same. Installed base of customers means everything for this strategy to work.

Intel wants Achronix asynchronous logic IP. This is believable. An FPGA friend of mine explained this to me and it made complete sense. Unfortunately it was very long winded and uber technical (this guy is from UC Berkley) so I could never do it justice, so I will leave it at that.

But this is all just false paths to throw the mainstream media off the track. The REAL reason Intel made this announcement:

A CHEAP SHOT AT AMD / GLOBALFOUNDRIES!

Intel is clearly feeling the heat from AMD, especially with the integrated CPU/GPU Llano chip coming out of the GlobalFoundries Dresden fab. Llano, the world’s first quad-core microprocessor with integrated DirectX 11 graphics processor, is made using 32nm silicon-on-insulator process technology with high-K metal gate (HKMG). Llano competes with Intel Corp’s much anticipated Sandy Bridge integrated microprocessor. Intel can be petty at times and this is one of those times, believe it!

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Semiconductor Forecast: 2010 Boom – 2011 Bust?

Semiconductor Forecast: 2010 Boom – 2011 Bust?
by Daniel Nenni on 10-15-2010 at 6:34 pm
Categories: Foundries, TSMC


Again, my economic bellwether is TSMC, and judging by the first half, 2010 will go down as one of the most profitable years the semiconductor industry has ever seen. In the 2[SUP]nd[/SUP] quarter the foundries again posted record breaking wafer shipments, revenues, and profits. 3[SUP]rd[/SUP] quarter foundry financials should be even stronger. Bottom line, the semiconductor industry will see its largest yearly expansion and will easily break the $300B barrier in 2010.
Pent up demand certainly explains the V recovery. My family was in financial lock down in 2009 but will more than make up the difference in 2010. New laptops, mobile phones, we even added a car and new energy efficient kitchen appliances, all semiconductor laden devices.

Unfortunately, TSMC CEO Morris Chang recently commented that “inventory levels of its fabless and IDM customers have increased at a rate close to the increase in sales.” Total semiconductor inventories did grow 10% in Q2 which is double what was forecasted. Customers of both TSMC and UMC reported high inventory sequential growth levels for the second quarter of 2010:

  • Qualcomm’s grew 11%
  • Broadcom’s went up by 21.6%
  • MediaTek’s jumped 24%
  • AMD’s rose 14%
  • TI’s climbed 10%


An August 5th post by Bill Jewel of Semiconductor Intelligence summarizes recent growth forecasts by the top analysts, which have risen dramatically month-to-month throughout 2010. Seriously, forecasting semiconductor growth this year has been like forecasting the weather, anything farther than 10 days out is just not reliable!

Bill however does not exactly follow my semiconductor Boom to Bust prediction in 2011:
Electronics new orders and production data from key countries also indicate a strong recovery.U.S.electronics new orders were up 14% in 2[SUP]nd[/SUP] quarter 2010 after showing a year-to-year decline of 14% in 2[SUP]nd[/SUP] quarter 2009. The European Union, Japan and Taiwan all had significant declines in electronics in early 2009, but have all bounced back to solid growth in 2010. China electronics production was the least affected by the recession, with 1[SUP]st[/SUP] quarter 2009 flat with a year ago. Chinahas recovered back to double-digit growth since 4[SUP]th[/SUP] quarter 2009.

Nor does Bill support my position on growing semiconductor inventories:

What about electronics inventories? Are they getting ahead of demand? Data from theU.S.andJapanshow the ratio of the inventory held by electronics manufacturers to their shipments began to climb in early 2008. The ratio peaked inJapanin December 2008 and then declined rapidly. In 2010, the ratio inJapanhas leveled off in the 80% to 90% range, below where it was in early 2008. TheU.S.ratio peaked in March 2009 and has declined to the 130% to 140% range, about the same level as the beginning of 2008.

Unfortunately, government stimulus packages are expiring and leading economic indicators: consumer confidence index (CCI), jobs, housing, etc… are in decline, which supports my 2011 semiconductor bust (back to single digit growth) prediction. Not that there is anything wrong that!
Hopefully the recent semiconductor foundry CAPEX surge will result in excess manufacturing capacity in 2012, which will in turn keep chip prices low. Remember, a modern GigaFab only has to run at 40% capacity to break even. Low chip prices will then support rampant consumerism and we will back to double digit semiconductor growth yet again. That’s my story and I’m sticking to it!

lang: en_US

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What Do You Mean by Mandatory?

What Do You Mean by Mandatory?
by glforte on 10-14-2010 at 6:00 pm
Categories: EDA, Foundries, Siemens EDA, TSMC

When TSMC and Mentor Graphics held a joint seminar for mutual customers to go over new DFM requirements at 45/40 nm, two customers basically asked the same question, “What do you mean by mandatory?” Of course, TSMC wasn’t going to stand over them and say, “Mandatory means mandatory, what part of mandatory don’t you understand?” :=) TSMC admitted that they hadn’t yet changed the tape-out checklist to forcibly include the DFM checks (CMP and LPC). This is what begs the question, what do you mean by mandatory?
Continue reading “What Do You Mean by Mandatory?”

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What Do You Mean by Mandatory?

What Do You Mean by Mandatory?
by glforte on 10-14-2010 at 6:00 pm
Categories: EDA, Foundries, Siemens EDA, TSMC

When TSMC and Mentor Graphics held a joint seminar for mutual customers to go over new DFM requirements at 45/40 nm, two customers basically asked the same question, “What do you mean by mandatory?” Of course, TSMC wasn’t going to stand over them and say, “Mandatory means mandatory, what part of mandatory don’t you understand?” :=) TSMC admitted that they hadn’t yet changed the tape-out checklist to forcibly include the DFM checks (CMP and LPC). This is what begs the question, what do you mean by mandatory?
Continue reading “What Do You Mean by Mandatory?”

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So, Why Not Just Write Better Rules?

So, Why Not Just Write Better Rules?
by glforte on 10-14-2010 at 4:00 pm
Categories: EDA, Foundries, Siemens EDA, TSMC

In my submission about TSMC making some DFM analysis steps mandatory at 45nm (see “TSMC’s DFM Announcement”), I ended with a question about why the foundries can’t just write better design rules (and rule decks) to make sure all designs yield well. Here’s my take on this complicated question.
Continue reading “So, Why Not Just Write Better Rules?”

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TSMC’s DFM Announcement

TSMC’s DFM Announcement
by glforte on 10-14-2010 at 4:00 pm
Categories: EDA, Foundries, Siemens EDA, TSMC

If you are a TSMC customer, no doubt you have heard TSMC is requiring lithography and planarity analysis for all 45nm designs. Their website says customers can either run it themselves, or contract TSMC services to do it. The most cost-effective way would be for the customers to run it themselves, but some might not have the resources to do that. Of course, by the time you pay TSMC to do it 3 or 4 times, you could have bought some tools and run it yourself. That’s good for Mentor and other EDA vendors, right? Probably, but there has to be more to it than that.
Continue reading “TSMC’s DFM Announcement”

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So, Why Not Just Write Better Rules?

So, Why Not Just Write Better Rules?
by glforte on 10-14-2010 at 4:00 pm
Categories: EDA, Foundries, Siemens EDA, TSMC

In my submission about TSMC making some DFM analysis steps mandatory at 45nm (see “TSMC’s DFM Announcement”), I ended with a question about why the foundries can’t just write better design rules (and rule decks) to make sure all designs yield well. Here’s my take on this complicated question.
Continue reading “So, Why Not Just Write Better Rules?”