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Intel
Posted on by Arie Lashansky

Hybrid Memory Cube and the Intel Knights Landing

Hybrid Memory Cube and the Intel Knights Landing
by Arie Lashansky on 08-07-2014 at 8:00 am
Categories: FPGA, Intel, IP, Xilinx

While looking for information on a Xilinx Spartan 6 Project with DDR memory I came across a new type of DRAM called the Hybrid Memory Cube (HMC). The technology made me want to take a closer look:

The Hybrid Memory Cube is like a stack of DDR chips stacked die on die using through silicon vias to interconnect the dies the bottom die in not a Dram but a logic Die.The major difference is that the block is not addressed in a way of Address and Data lines like the traditional Jedec memory but in a High speed serial IO like PCI Express.

Think of the cube as Four High Speed Serial Links or 16 lanes. The Hybrid Memory Cube has far better bandwidith as it can be addressed by 4 different High speed links. Each serial lane can run at 10GBps, 4 lanes make a link of 40GBps, in a chip with 4 links it is 160GBps.

From what I can see the (HMC) is is a game changer for memory:

[LIST=1]

  • The footprint vs memory density is far smaller as 8 dies Stacked
  • The Logic Die at the bottom of the stack takes the memory loading away from the CPU
  • The PCB may be easier to Route as no need for all data address and clocks to have the same timing as the data is serial (PCI compaired to PCI Express).
  • The link between the memory and the CPU becomes more abstract as the CPU does not have direct control over the memory via a logic device at the bottom of the stack. I’m not sure this is an advantage and does not have a way to make one memory call a high priority on a different one. (Not a real world problem at such High speeds). The logic controller (Bottom die) can also change the order in which the memory responds to calls.
  • Concurrency as each lane can pass requests to the cube so at the same time the cube may be reading two different memory locations

    An example of where HMC will be used is The Knights Landing chip from Intel. Looking at Knights Landing lets say each Atom core is connected a lane that means 16 cores work on one shared address space.That I think may be the 4 memory chips in front .The two at the back I see may have each core connected to a link (4 lanes)
    http://en.wikipedia.org/wiki/Xeon_Phi 72 atom chips on one die at 14nm.
    Note 32 GDDRS both on front and Back of the Knights Corner below Knights Landing will not look like this with 6 HMC mounted on the interconnectsubstrate modules one chip does the work of the whole Board.

    Intel’s current chip is the Family Knights Corner, the same Basic Idea as Knights Landing but far less Features with DDR5 and not HMC.

    http://ark.intel.com/products/codename/57721/Knights-Corner

    https://www-ssl.intel.com/content/www/us/en/processors/xeon/xeon-phi-coprocessor-datasheet.html

    The only way I can see to use the HMC memory seems to be by using a FPGA solution. Both Xilinx and Altera have IP partners (see the Video’s Below):

    Micron Talk at Hot Chips: http://www.hotchips.org/wp-content/uploads/hc_archives/hc23/HC23.18.3-memory-FPGA/HC23.18.320-HybridCube-Pawlowski-Micron.pdf

    https://www.youtube.com/watch?v=QOYE56OCE3o     (After minute 26:50 to 1:05 J. Thomas Pawlowski explains HMC)

    Xilinx Demo: https://www.youtube.com/watch?v=GYpJqDYpuG4

    Altera Demo: https://www.youtube.com/watch?v=oMsWRr0eBg4

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