Last Monday Daniel Nenni and I had a conference call with Jason Gorss and Shubhankar Basu of Global Foundries to get an update on their 14nm process. Shubhankar is the product line manager for 14nm.
Global Foundries 14nm process is a FinFET on bulk process they licensed from Samsung and both companies supply the same process although as Shubhankar pointed out they have different targets for the process especially in light of Global acquiring IBM’s chip business.
The 14nnm process is run in Global’s Fab 8 in upstate New York. The 14LPE process was the first generation and was qualified in January. A second generation 14LPP process was qualified in September. They are now shipping 14nm parts to customers.
Shubhankar said that Global is being successful at getting customers to design for their 14nm process and aren’t just a “second source”. In the mobility space a lot of consumer parts need high performance. Global has a huge IP library for LPE and LPP and they are having success in mobile diversifying their customer base.
14LPE and 14LPP share the same design rules and most of the equipment is the same. 14LPP offers a 10% to 14% performance boost over 14LPE. The Back-End-Of-Line (BEOL) is the same but 14LPP has some transistor enhancements. I asked about the transistor enhancements and Shubhankar said he couldn’t give specifics. I mentioned enhancements such as taller fins. Shubhankar would only comment that you can make geometry enhancements and you can reduce parasitic by tailoring things such as implants.
My analysis of his comments is as follows: He did say the pitches are the same so my guess would be a combination of taller fins and implant adjustments. This would suggest to me that manufacturing costs aren’t very different for LPE and LPP. Taller fins would require a longer etch and likely have some yield impact but I would expect the costs to be similar, say within 10% (just my opinion). I also think this is basically what TSMC did with 16FF and 16FF+, 16FF+ is a tuned version.
Production qualification is greater than 60% yield on a 128Mb SRAM. Yields on LPP are >20 points higher than that now (>80%) and LPE is ahead of that.
Daniel mentioned that processes used to be performance first but are now mobile-power first. He asked how the FPGA and processor guys get what they want.
Shubhankar notes that FinFET changes the game, performance is so much better versus planar that it is a no brainer. Further the 3D FinFET structure has much lower leakage than planar (fully depleted). Their IP is also characterized for high performance.
Shubhankar believes 14nm will be a long lived node, there is a lot more to be gotten out of it, they aren’t standing still. I asked him if this would be like what we see at 28nm where companies such as TSMC have HP, HPL, HPM, LP, HPC and other variants. He said they would continue to tune performance and cost and that tier two and even tier three customers are adopting the process.
I asked how they segment 14nm versus the 22nm SOI family Global recently announced. Shubhankar said that certain IOT applications that are middle spectrum or on the lowest end of mobility are still on 28nm and reluctant to move to FinFETs. 22nm SOI is an intermediate process and can be pushed close to FinFFET performance. You can also run 22nm SOI at 0.4 volts and 14LPP is not ready for that space yet.
In terms of cost a 22nm SOI wafer is less expensive than a 14nm FinFET wafer but die cost depends on how much shrink you can get. Some die will be cheaper in 22nm SOI and some die will be cheaper in 14nm FinFET if you get enough die size shrink. If you need the longest battery life and performance is less important 22nm SOI wins, if you need maximum performance 14FF wins.
Daniel commented that Qualcomm and others are doing server chips. Will a foundry do a very high performance process for server chips. This led to a discussion about the IBM chip business acquisition and whether IBM’s 14nm FinFET on SOI process will be available to outside customers. Global is committed to support IBM’s SOI technology for 10 years but beyond that they can’t comment on IBM technology plans although they did say they think it is a game changer.
My analysis: An interesting thing here is IBM’s 14nm FinFET on SOI process is a server process with embedded DRAM for very large on-chip cache. This could potentially be an interesting process for very high performance applications if Global could or would offer it externally. Once again this section is just my opinion, they wouldn’t comment on this.
Daniel also commented that he thinks 10nm will be kind of a short node like 20nm because 10nm and 7nm will use the same equipment (the same way that 20nm and 16nm used the same equipment).
More information HERE.
Follow the adventures of SemiWiki on LinkedIn HERE!
Share this post via:
AI Semiconductor Market