EUV: the view from imec

I’m at the 2015 imec technology forum (ITF) in Brussels the next few days. One of the presentations today was by Peter Wennink, the CEO of ASML. The thing that most interested me in his presentation is what the status of EUV is today. ASML is the only company developing EUV steppers so what they think is important. On the other hand, they are the company building the steppers so what they say has to be looked at with some skepticism. First, what Peter said.

The motivation for EUV is that without it we will need increasingly multiple patterning. He pointed out that the biggest problem is not even the number of mask steps but the number of overlay metrology steps which goes up even faster. But EUV has to work at 7nm. It is already too late for 10nm, the plans are already set at least for the introduction. And 5nm will require double patterning even with EUV.

Since this time last year, EUV has made huge progress:

• Productivity requirement 1000 wafers/day

  • using 80W source printed 1022 wafers in 24 hours at one customer
  • 110W power demonstrated at ASML
• Availability 70%

  • 55% average at multiple sites
  • 82% for one week achieved at one customer
  • sustained source availability about 85% on track for end of 2015
• System shipments in 2015: 6

  • integration of multiple systems in progress at ASML
  • 2 systems on order intended for production
  • volume purchase agreement with one customer (presumed by everyone to be Intel) for 15 systems of which 2 ship in 2015

Next issue, the pellicle. Clean scanner remains a priority and they are on track for 10X per year reduction in front-side defects (basically contamination from the light source or other parts of the scanner getting onto the mask, which is actually a mirror).

ASML started their own pellicle program since the traditional pellicle manufacturers were not interested. They now have a full size pellicle that covers the whole mask. Transmissivity is 85% (in one direction, the light has to go through twice though: reflective mask remember). No impact on alignment.

Inspection is a problem. Pellicle is not transparent to either visible light or e-beam so it has to be removed for mask inspection, and then replaced after inspection. Pellicle is compatible with both the mask flow and the scanner.

So it all sounds great right? Here are problems that people at the conference told me about during dinnner and breaks.

So what are the next problems?

• Problems are being solved linearly. Until light source is working, nobody is worrying too much about all the other problems. Everything has to work perfectly by about 2017 if it is to be on schedule for 7nm. The equipment cannot be changed after start of qualification which is about 2 years before volume is ramped fully
• Pellicle inspection. With transmissive masks, the mask can be inspected, then the pellicle added and then a final inspection done through the pellicle. With EUV can’t do that. So if a particle gets trapped under the pellicle it will print and thousands of wafers may be wasted. Currently no way to inspect unless EUV light is used but no inspection equipment like that has been developed
• Heat. The light source is up to 110W and desired to go to 250W. The mirrors absorb about 30% of energy so they will get really hot. The mirrors are made of silicon molybdenum alternating layers but they have different coefficients of expansion and delaminate around 150C. Also, the mask is early in the light path and absorbs a lot of energy but must not distort or it will cause printing errors
• Mask blanks are not defect free. Before adding the silicon molybdenum layers the defects are too small to see with visible light, and after they are get bigger as the mirror is built up. By the time they are visible it is too late to do anything about it. Currently no good way to fix a defect on the mask blank before patterning

If all this gets fixed and EUV is commercially viable then we should get back on track for the 40% node to node reduction in cost, which is basically an increase in node to node cost per wafer of around 20% combined with a doubling of the number of transistors per area.