Extending Moore in Silicon

A year ago many eulogized the death of Moore’s Law at 28nm due to higher prices per transistor at more advanced nodes, but now that we have celebrated the 50th anniversary let’s look ahead to technology scaling and electronic systems miniaturization for the next decade. Despite our industry’s bipolar tendencies and daunting technical challenges, I remain soberly optimistic about the future of semiconductors. Here is one reason why:

“The technology shift from planar to 3D MOSFETs has created new opportunities for disruptive device and process innovations that can extend Moore’s Law.” –Jeff Wolf, CEO of FinScale Inc.

Has technology scaling brought us into a physical domain where new approaches are needed? Many think so, and it seems counter-intuitive (to me) that we could capture all of the potential gains offered by the shift to 3D MOSFETs using the industry’s now institutionalized tick-tock approach to device and process development. A break from past paradigms should be explored when transitioning from two to three dimensions in any context – as we’ve already experienced in graphics, CAE and video games.

I recently met with founders of FinScale, a device and process innovation start-up, who introduced me to their 3D quantum FinFET. As CTO Victor Koldyaev described how FinScale’s qFinFET harnesses positive quantum effects and mitigates negative QE, I had to stop him and ask, “Do you really talk to customers like this?” It was refreshing to hear scientific support for how we can continue to scale forward with Moore’s Law benefits, and made me realize we haven’t been getting as much technical explanation from manufacturers about their process and yield improvement learning as in the past.

We should expect changes in the way we describe semiconductor technology in the quasi-ballistic regime. I don’t yet hear many talking about the fundamentals of sub-20 nm 3D MOSFET operation, which are increasingly dominated by the atomic properties of materials and quantum effects. Beyond our vital discussions about litho, punch-through and electrostatic control, I’m looking forward to hearing more discussions about quantum inversion layers, ballistic transport, scattering centers and carrier relaxation times.

FinScale touts qFinFET’s many-node Moore’s Law scaling roadmap in silicon down to the 5 nm node, on either bulk or SOI, with dimensions specified for critical device features at each node. The FEOL process sequence is defined, including many FinScale innovations that work together to improve performance, density and power efficiency, and lower the manufacturing cost of fin-based devices. FinScale claims that qFinFET can be readily fabricated using existing advanced node process modules, equipment and materials, and provide fin-based device solutions for logic, embedded and stand-alone memories, analog, RF and image sensors.

While this all sounds good and is well-supported by scientific and advanced manufacturing technology research, FinScale’s inventions need to be validated in practice by a high-volume foundry or IDM early adopter, which is FinScale’s goal.

I think a compelling case can be made for start-ups as enablers of the industry’s path forward – to incubate potential breakthroughs with focused intensity on accelerated timelines. The figure below shows the recent results for the all-in-house approach to R&D. For the past five years the time gaps between node-to-node transitions at leading manufacturers are increasing. It doesn’t appear that business-as-usual is getting the industry to where it needs to be according to Moore. These gaps are opportunities that FinScale aims to fill.

I’m encouraged to see renewed investment interest in semiconductor start-ups after declining deal flow in recent years. Our industry needs to keep seeding and cultivating promising start-ups and disruptive technologies so that they’re ready when needed to solve difficult challenges and capitalize on tomorrow’s world-changing opportunities.