Advances in Nanometer Analog and Mixed Signal Design!

Advances in Nanometer Analog and Mixed Signal Design!
by Daniel Nenni on 04-13-2015 at 10:00 pm

 Mentor’s annual user group meeting at the Doubletree Hotel in San Jose, CA is coming up on Tuesday, April 21[SUP]st[/SUP]. This complementary event provides a unique opportunity to share design techniques and exchange ideas with other users and experts in the design community. As you may have read I am the star of the show; moderating a panel on The Changing Foundry Landscape: Trends and Challenges. But there are some other events there that should be of interest. And did I mention this is a complementary event with complementary food and complementary drink? The Doubletree puts out a nice spread, absolutely.

Featured Sessions – Analog/Mixed-Signal (AMS) Verification Track

Advances in Nanometer Analog/RF/Mixed-Signal Verification
Presented by: Ravi Subramanian Ph.D., General Manager – AMS Verification, Mentor Graphics
The analog, mixed-signal, and RF (AMS/RF) content of semiconductors is growing faster than any time in history, and is at the center of the semiconductor industry’s next major cycle. This wave is largely being driven by the rise of nanometer mixed-signal application specific standard products (ASSPs) targeted at new consumer, mobile, automotive, IoT, and datacenter applications. Performance targets for PLLs, ADCs, I/O circuits, PHY transceivers, image sensors, and embedded memories are becoming more stringent in the presence of higher device noise, lower supply voltages, less predictable process corners, and ever-increasing parasitics. This talk introducesimportant proven new approaches that have been successfully deployed in leading design teams to help analyze a variety of physical and electrical effects- spanning parasitics, coupling, noise, distortion, variability, power etc. – via innovative circuit analysis techniques. Specific case studies will be shown to illustrate the approaches used to target specific problems, and the underlying technology to help achieve this success.

Remember, Ravi was CEO of Berkeley Design Automation when they were acquired by Mentor. Ravi is very approachable and you will not meet another semiconductor executive with more hours logged in front of customers and partners. I worked closely with Ravi managing the strategic foundry relationships for BDA up until the acquisition so yes I know this by experience.

Device Noise Analysis of Precision Analog Circuits with the Analog FastSPICE Platform
Presented by: Dr. Boris Murmann, Associate Professor, Stanford University
Device noise, including thermal and flicker noise, are significant limiters on the performance of precision analog circuits and in particular in switched-capacitor circuits found in CMOS mixed-signal ICs. This paper reviews design challenges with these circuits from a theoretical perspective and provides best practices and simulation examples using the Mentor Analog FastSPICE (AFS) Platform. AFS delivers foundry-certified SPICE accuracy with industry-leading performance and full-spectrum device noise analysis. Circuits discussed range from track-and-hold circuits, to integrators, to SC delta-sigma ADCs.

I have worked with Boris before and will see him again at the EDPS Workshop panel I’m chairing next week: FinFET vs FDSOI – Which is the Right One for Your Design? It is all about WHO you know in this industry and you should definitely get to know Boris.

Design and Circuit Verification Challenges of Inter-Die Interfaces for 2.5D/3D IC Architectures
Presented by: Miguel Miranda Corbalan Ph.D., Staff Engineer, Qualcomm
One of the key challenges in 2.5D/3D IC architectures is the high-speed I/O interface between multiple dies/tiers. The design and characterization of these interfaces have significant circuit verification accuracy and performance requirement in order to achieve data rate and signal integrity specifications on par with single die SoC implementations. Challenges over and above single die implementations include power and signal integrity control over off-die interconnect structures. This paper describes the nanometer circuit verification requirements for power and signal integrity verification of a high-speed two die system. We present results from the methodology deployed at Qualcomm® using the Analog FastSPICE™ Platform from Mentor Graphics®. This methodology resulted in SPICE accurate simulation results, validated versus silicon measurements, with 4x speed-up compared to a traditional multi-threaded SPICE simulator enabling the successful verification and optimization of the high-speed I/O architecture.

I have not met Miguel but we are connected on LinkedIn so he has that going for him.

Verification of Mixed-Signal Interaction of Analog-Centric ICs
Presented by: Senthil Vinayagam, Principal Design Engineer, Cobham Semiconductor Solutions
Analog-Centric ICs used in automotive, aerospace, defense, and medical applications have become more and more mixed-signal designs with analog functions strongly coupled with complex digital control logic. The interaction between analog and digital blocks in these ICs can include feedback loops that pose a significant verification challenge. Traditional methodologies, verifying separately the functionality of the analog and digital blocks, is no longer sufficient and may leave hidden-bugs in the IC undetected, resulting in silicon re-spins. This presentation describes the verification of an ADC, designed for high-reliability telecommunication and imaging applications, using the Eldo circuit simulator and Questa ADMS mixed-signal simulator from Mentor Graphics.

I do not know Senthil nor are we LinkedIn but you can count me in on anything automotive or medical.

Featured Keynotes

  • “Secure Silicon: Enabler for the Internet of Things”

Presented by: Wally Rhines, Chairman & CEO, Mentor Graphics

  • “Mega Trends Driving Architectures of Mobile Computing and IoT devices”

Presented by: Karim Arabi, VP of Engineering, Qualcomm

View Agenda
andRegister Today!


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