Bug Hunting in NoCs. Innovation in VerificationDespite NoCs being finely tuned in legacy subsystems,…Read More
Alphawave Semi Unlocks 1.2 TBps Connectivity for HPC and AI Infrastructure with 9.2 Gbps HBM3E SubsystemIn the rapidly evolving fields of high-performance computing…Read More
Elevate Your Analog Layout Design to New HeightsAnalog IC layout is a demanding endeavor as…Read More
Analog Bits Momentum and a Look to the FutureAnalog Bits is aggressively moving to advanced nodes.…Read More
Spatial audio concepts targeted for earbuds and soundbarsSpatial audio technologies deliver more realistic sound by…Read More
Very interesting question from Zahrein in this thread: “how to manage an embedded USB 3.0 PHY Verification”? To clearly position the problem, Zahrein need to run the RTL verification of a complete SoC integrating an USB 3.0 function, that is the Controller (digital) and the PHY (Analog Mixed Signal) embedded in the SoC. The question,… Read More
EDA companies and foundries must closely collaborate in order to deliver IC tool flows that work without surprises at the 40nm and 28nm nodes.
Tomorrow in San Jose you can attend this 4th annual event hosted by TSMC along with Mentor Graphics and other EDA and IP companies.
Here are some of the topics that will interest IC designers… Read More
Every SOC that is designed must be tested and the premier conference for test is ITC, held last month in Anaheim, California.
I spoke with Robert Ruiz of Synopsys by phone on September 21st to get an update on what is new with EDA for test engineers this year. Robert and I first met back at Viewlogic when Sunrise was acquired in the 90’s.… Read More
If you follow the SemiWiki Twitter feed you may have noticed that The Motley Fool (Seth Jayson) did three more articles on TSMC financials. The first Foolish article was blogged on SemiWiki as “TSMC Financial Status and OIP Update”.
The next three Fool Hardy articles look at cash flow (the cash moving in and out of a business), accounts… Read More
Don’t forget the SpringSoft Community Conferences next week in Austin on Tuesday and in San Jose on Thursday. There is no charge and you even get a free lunch (see “no such thing as…”).
The morning in Austin is focused on functional closure and how to leverage SpringSoft’s verification technology… Read More
At the TSMC Open Innovation Platform Ecosystem Forum (try saying that three times in a row) next week (on Tuesday 18th), Atrenta will present a paper on the TSMC soft IP qualification flow. It will be presented by Anuj Kumar, senior manager of the customer consulting group.
More and more, chips are not put together what we think of … Read More
Using the “Diffusion of Innovation” theory, we have built a forecast for the market of USB 3.0 IP in 2011-2015. In this new version of the report, we have inserted the actual revenues generated by USB 3.0 IP from different vendors, for 2009 and 2010, and reworked the 2011-2015 forecast. Initially, we had expected this IP market to … Read More
Intro
My first exposure to hardware prototyping was at Intel back in 1980 when the iAPX 432 chip-set group decided to build a TTL-based wire-wrap prototype of a 32 bit processor to execute the Ada language. The effort to create the prototype took much longer than expected and was only functional a few months before silicon came back.… Read More
Time to ring the Bell. With the iPhone 4S, Apple has just surpassed the 70% gross margin metric that usually equates to a compute platform becoming an industry standard. IBM’s mainframe achieved it in the 1960s with the 360 series and still is able to crank it out with their Z-series. The combined Intel and Microsoft tandem (Wintel)… Read More
In case you have not heard, the 16th Si2-hosted conference highlighting industry progress in design flow interoperability comes to Silicon Valley (Santa Clara, CA) on October 20th. Si2Con will showcase recent progress of members in the critical areas of:
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Intel’s Death Spiral Took Another Turn