Intel Wildcat Lake: Right-Sizing Silicon Without Sinking PerformanceLance Hacking, Intel Intel Core Series 3, code-named…Read More
Optimizing for Thermoelastic in Package and PCB Design from the OutsetSignoff-quality design tools are mandatory for signoff, though…Read More
Avestra: Agentic AI for SystemVerilog Assertion GenerationModern ASIC, SoC, CPU, and GPU development depends…Read More
Silicon dominates our lives, CPU’s, GPU’s are in the limelight but the unsung hero is the FPGA. They simply do the work where other silicon dare not tread, as they are unfit for the task. Never send a boy to do a man’s job.
For a moment, if we can, just for a few minutes perhaps we can break away from the social media bubble… Read More
We have already discussed the recently released M-PCIe ECN from PCI-SIG in Semiwiki at the end of 2012, but the new “standard” (in fact an Engineering Change from PCI-SIG and MIPI Alliance) was only real on paper, at that time. The upcoming webinar from Synopsys, M-PCIe: Utilizing Low-Power PCI Express in Mobile Designs, shows … Read More
It now appears that Steve Ballmer was suddenly given his walking papers at the urging of an activist investor (ValueAct) and with the concurrence of Bill Gates. Wall Street’s growing impatience tends to coincide when the Innovators Dilemma scenario has taken hold of a company that has been unable to overcome its challengers. Why… Read More
It looks to me as if Ballmer’s planned resignation from Microsoft is going to leave Nokia high and dry without an operating system. Because any successor to Ballmer will cancel Windows Phone which has managed to take Microsoft’s penetration in smartphones from 5% before it had a serious partnership with Nokia all … Read More
LSI is an early adopter of Formality Ultra, Synopsys’s tool for improving the entire ECO flow. I already wrote about the basic capability of the tool here. ECOs are changes that come very late in the design cycle, after place and route has already been “nearly” completed. They occur either due to last minute spec… Read More
Perhaps no area in EDA has been as enigmatic as high-level synthesis (HLS). At nearly every industry event, some new-fangled tool always seems to be tabbed as the next big thing by some analyst or pundit. In a twist, the latest news is on one of the oldest tools – CybeWorkBench.… Read More
Estimating the MTBF of an SoC should always include an analysis of synchronizer reliability. Contemporary process nodes are introducing new challenges to the reliability of clock domain crossings so it is prudent to revisit how your simulation tool calculates a synchronizer’s MTBF. Let’s list the ten most common pitfalls.… Read More
I remember during my first ten years as a software developer, I used many different computers such as IBM mainframes, Apollo and Sun workstations, and VAX computers. During that time I also bought my first home computer, a Macintosh. I didn’t of course think of this at the time, but the one thing they all had in common was that they did… Read More
The TSMC Open Innovation Platform® (OIP) Ecosystem Forum brings TSMC’s design ecosystem member companies together to share with our customers real-case solutions for customers’ design challenges and success stories of best practice in TSMC’s design ecosystem.
More than 90% of the attendees last year said “this… Read More
I attended the semi-annual SEMI Silicon Valley Lunch meeting last week. The semiconductor equipment people are the ones that really know what is going on. People can talk about capex numbers on conference calls but it is the equipment vendors who either do or do not get orders for particular types of equipment. In turn, the analysts… Read More
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