Webinar: Faster Design Spec to Implementation using IP-XACTAs SoC design flows grow increasingly complex, IP-XACT…Read More
Webinar: Caspia Shows You How to Fix Security Flaws Before It’s Too LateI recently posted an overview of an upcoming…Read More
Feed Forward Intelligence: Enabling Testability in the Chiplets EraThe semiconductor industry is entering a new era…Read More
Synopsys Unifies Electrical, Thermal, Mechanical, and Optical Analysis with Multiphysics Fusion Solutions Market Leaders Including Cisco,…Read More
RISC-V and AI: The Architecture Shift Is NowThe semiconductor industry has experienced several defining transitions…Read More
Eric Peersfounded Missing Link tools in 2008 and his company was acquiredby Methodics in 2012, so I met with him at DAC to understand how their EDA tools for Design, Test and Regression Management are used in an SoC design.
Eric Peers, Methodics… Read More
At DAC you can measure buzz by how many people are crowded into your booth. I saw a crowd at the Oasys booth, so stopped to take in their 10 minute overview presentation. Here’s what I learned.… Read More
Most EDA start-up companies have a narrow product focus to complement existing tool flows, however Invarian is taking a much bolder approach by offering tools for:
Berkeley DA coined the phrase “Analog FastSPICE”, and I’ve been getting an update from them at DAC for several years now. In Austin I met with Paul Estradathe COO and Patrick Muyshondt.
Paul Estrada
Paul Estrada, COO (circa 2010)
… Read More
I love it when EDA companies send their engineers to DAC because I learn more of the unvarnished truth about their products. I met with Bill Thomas of Aldec to get an update on their HW prototyping boards, then two NEC engineers to learn about High Level Synthesis.
HW Prototyping
Bill Thomas, Research Engineer at Aldec
… Read More
Last year I was surprised at DAC by an un-heard of EDA company from China, ICScape. This year I followed up and spoke with Ravi Ravikumar about what’s new with ICScape in 2013.… Read More
The building blocks for every SoC are standard cell libraries that are assembled, designed and verified together. But how do we really know if all the data formats used during design are correct and consistent? To answer that question I spoke with Johan Peetersof Fractal Technologiesat DAC.
Johan Peeters, Rene Donkers
… Read More
The smaller the process node the more necessary it is that you extract accurate parasitics from interconnect and 3D structures in order to analyze timing, thermal effects and ESD compliance. Silicon Frontlinehas EDA tools in all three of these categories, so I met with Dermott Lynchat DAC to get an annual update.
Dermott Lynch,… Read More
I listened to Dan Niles’s quarterly report that he does for GSA. He had a lot of the usual background data on savings rates and GDP growth, but the big story is that everything changed on May 22nd and that this will turn out to be a very significant moment. That was the day that the Fed basically announced that it would start to “taper”… Read More
Aart de Geus gave one of the visionary look to the next 50 years of EDA as a warmup to Stephen Wu’s keynote. EDA is enabling the greatest push-pull ever, part of an exponential change on a scale never before seen.
Technologies seem to go through a 50 year technical push phase (driven by improving the technology) followed by a 50… Read More
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Available Is Not In Control: Balancing Output, Quality, and Risk in High-Volume Fabs