How I learned Formal VerificationBing Xue is a dedicated Formal Verification Engineer at Axiomise,…Read More
Accellera 2024 End of Year UpdateFrom my viewpoint, standards organizations in semiconductor design…Read More
Synopsys Brings Multi-Die Integration Closer with its 3DIO IP Solution and 3DIC ToolsThere is ample evidence that technologies such as…Read More
One year ago I met with Hany Elhak of Synopsys to get an update on what was new with HSPICE in 2011, so this year at DAC Hany met me at the Synopsys booth for a quick update.
HSPICE has something called Precision Parallel so with 16 cores your IC circuit simulations will have about 10 x speed up compared to a single core.… Read More
For a small company, Solido has some very large customers and partners, TSMC being on of them. Why? Because of the high yield and memory performance demand on leading edge technologies, that’s why.
Much has been made of and will continue to be said on the march of Moore’s Law. While economics of scale and performance vs. power… Read More
Tuesday morning at DAC I attended the Synopsys-hosted breakfast to hear from foundries and ARM about the challenges of designing and delivering silicon at the 32nm/28nm and 20nm nodes.
… Read More
As I mentioned in a previous blog Cadence Update 2012, Martin Lund is now in charge of the Cadence IP strategy. Martin read my first blog and wanted to exchange IP strategies so we met at DAC 2012 for a chat. Not only did Martin connect with me on LinkedIn, he also joined the SemiWiki LinkedIn group, which now has 4,000+ members. So yes,… Read More
News today is that Moody’s has downgraded Nokia to junk status. They also announced that they will lay off 10,000 people (including about 1 in 4 of the people they employ in Finland, where Nokia is headquartered).
For those of you who don’t know all the inside-baseball stuff about Nokia, here is a recent little history.… Read More
Ciranova presented a hierarchical custom layout flow used on several large advanced-node designs to reduce total layout time by about 50%. Ciranova itself does automated floorplanning and placement software with only limited routing; but since the first two constitute the majority of custom layout time, and strongly influence… Read More
I got an email from Mentor Embedded this morning about a webinar on Implementing a GENIVI-compliant System. I have to admit I had no idea what GENIVI is, which surprised me. I spent several years working in the embedded space and so I usually have at least a 50,000 foot view of most things going on there. One reason for my ignorance is … Read More
Semiconductor manufacturing equipment has returned to growth after a falloff in the second half of 2011. Combined data from SEMI (U.S. andEuropean companies) and SEAJ (Japanese companies) show billings peaked at a three-month-average of $3.2 billion in May 2011. Bookings and billings began todrop in June 2011, with billings… Read More
Black Swan Events are not to be embraced, they are to be feared, if conventional wisdom holds true. And yet, the 2011 Black Swan that slammed the PC market (i.e. the Thailand Floods that wiped out a large part of the disk drive market) has turned out to be the key catalyst for reshaping the semiconductor industry in 2012 and 2013. Instead… Read More
Firas Mohamed, President and CEO (Ph.D.) of Infiniscale met with me on Monday at DAC to provide an overview of what EDA software they offer to IC designers at the transistor-level.
Vision – analog flow that Monte Carlo simulation is required, which is thousands of circuit simulations, however the higher the sigma the more… Read More
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