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NVM IP: Novocell Semiconductor has announced an expansion of their product line

NVM IP: Novocell Semiconductor has announced an expansion of their product line
by Eric Esteve on 07-08-2012 at 3:52 am

Novocell Semiconductor, core antifuse-based OTP Smartbit™ technology was first patented in 2001 and 2002, and created a solid foundation for the first ten years,” stated Walt Novosel, President and CTO, “Since then, our customer-driven focus has led to numerous innovations in our original high reliability Smartbit-based… Read More


Intel Goes Vertical to Guarantee PC Growth

Intel Goes Vertical to Guarantee PC Growth
by Ed McKernan on 07-07-2012 at 8:30 pm

A Bloomberg article from early July caught my eye as it portends further changes in the competitive mobile market landscape. Intel is now in the business of paying Taiwanese panel suppliers to ensure the supply of touch-screen panels for PC ultrabooks. In essence it says that to win in the PC market, Intel has to mimic Apple and go … Read More


Intel’s finfets too complex and difficult?

Intel’s finfets too complex and difficult?
by Tom Dillinger on 07-07-2012 at 7:00 pm

Thanks to SemiWiki readers for the feedback and comments on the previous “Introduction to FinFET Technology” posts – very much appreciated! The next installment on FinFET modeling will be uploaded soon.

In the interim, Dan forwarded the following link to me “ Intel’s FinFETs too complicated and difficult, says Read More


TSMC: Production Proven Design Services Driving SoC Innovation!

TSMC: Production Proven Design Services Driving SoC Innovation!
by Daniel Nenni on 07-06-2012 at 8:30 pm

One of the truisms of today’s disaggregated semiconductor design and manufacturing model is counter-intuitive to the do-it-yourself focus that is at the heart of every engineer. And yet, time and time again, success rewards those who understand that with today’s ever increasing complexity, it is difficult, if… Read More


Mind the Gap — Overcoming the processor-memory performance gap to unlock SoC performance

Mind the Gap — Overcoming the processor-memory performance gap to unlock SoC performance
by Sundar Iyer on 07-06-2012 at 3:25 pm

Remember the processor-memory gap— a situation where the processor is forced to stall while waiting for a memory operation to complete? This was largely a result of the high latency required for off chip memory accesses. Haven’t we solved that problem now with SoCs? SoCs are typically architected with their processors … Read More


Cadence at Semicon West Next Week: 2.5D and 3D

Cadence at Semicon West Next Week: 2.5D and 3D
by Paul McLellan on 07-05-2012 at 5:32 pm

Next week it is Semicon West in the Moscone Center from Tuesday to Thursday, July 10-12th. Cadence will be on a panel session during a session entitled The 2.5D and 3D packaging landscape for 2015 and beyond. This starts with 3 short keynotes:

  • 1.10pm to 1.25pm: Dr John Xie of Altera on Interposer integration through chip on wafer on
Read More

Minitel Shuts Down

Minitel Shuts Down
by Paul McLellan on 07-05-2012 at 5:02 pm

When I first came to the US, one project that we had going on at VLSI Technology was an ASIC design being done by a French company called Telic. The chip would go into something called “Minitel” which the France Telecom (actually still the PTT since post and telecomunications had not yet been separated) planned to supply… Read More


IC Design at Novocell Semiconductor

IC Design at Novocell Semiconductor
by Daniel Payne on 07-05-2012 at 12:09 pm

In my circuit design past I did DRAM work at Intel, so I was interested in learning more about Novocell Semiconductor and their design of One Time Programmable (OTP) IP. Walter Novosell is the President/CTO of Novocell and talked with me by phone on Thursday.… Read More


Managing Differences with Schematic-Based IC Design

Managing Differences with Schematic-Based IC Design
by Daniel Payne on 07-02-2012 at 2:41 pm

At DAC in June I didn’t get a chance to visit ClioSoft for a product update so instead I read their white paper this week, “The Power of Visual Diff for Schematics & Layouts“. My background is transistor-level IC design so anything with schematics is familiar and interesting.

The Challenge
Hand-crafted … Read More


IC Test Sessions at SEMICON West 2012

IC Test Sessions at SEMICON West 2012
by Beth Martin on 07-02-2012 at 1:43 pm

SEMICON West is coming up this July 10-12 at the Moscone Center in San Francisco. It covers a broad swath of the microelectronics supply chain, but I was particularly interested in the test sessions. Here are two that I recommend.

The Value of Test for Semiconductor Yield Learning” on Tuesday, July 10, at 1:30p. The… Read More