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Changing your IC Layout Methodology to Manage Layout Dependent Effects (LDE)

Changing your IC Layout Methodology to Manage Layout Dependent Effects (LDE)
by Daniel Payne on 04-18-2012 at 12:38 pm

Smaller IC nodes bring new challenges to the art of IC layout for AMS designs, like Layout Dependent Effects (LDE). If your custom IC design flow looks like the diagram below then you’re in for many time-consuming iterations because where you place each transistor will impact the actual Vt and Idsat values, which are now a … Read More


ARM Seahawk

ARM Seahawk
by Paul McLellan on 04-17-2012 at 8:27 pm

I wrote on Monday about ARM’s Processor Optimization Packs (POPs). In Japan they announced yesterday the Seahawk hard macro implementation in the TSMC 28HPM process. It is the highest performance ARM to date, running at over 2GHz. It is a quad-core Cortex A15.

The hard macro was developed using ARM Artisan 12-track libraries… Read More


Previewing Intel’s Q1 2012 Earnings

Previewing Intel’s Q1 2012 Earnings
by Ed McKernan on 04-17-2012 at 9:15 am

Since November of 2011 when Intel preannounced it would come up short in Q4 due to the flooding in Thailand that took out a significant portion of the HDD supply chain, the analysts on Wall St. have been in the dark as to how to model 2012. Intel not only shorted Q4 but they effectively punted on Q1 as well by starting the early promotion… Read More


Laker Wobegon, where all the layout is above average

Laker Wobegon, where all the layout is above average
by Paul McLellan on 04-17-2012 at 4:00 am

TSMC’s technnology symposium seems to be the new time to make product announcements, with ARM and Atrenta yesterday and Springsoft today.

There is a new incarnation of Springsoft’s Laker layout family, Laker[SUP]3[/SUP] (pronounced three, not cubed). The original version ran on its own proprietary database.… Read More


Soft Error Rate (SER) Prediction Software for IC Design

Soft Error Rate (SER) Prediction Software for IC Design
by Daniel Payne on 04-16-2012 at 10:00 am

My first IC design in 1978 was a 16Kb DRAM chip at Intel and our researchers discovered the strange failure of Soft Errors caused by Alpha particles in the packaging and neutron particles which are more prominent at higher altitudes like in Denver, Colorado. Before today if you wanted to know the Soft Error Rate (SER) you had to fabricate… Read More


Atrenta’s Spring Cleaning Deal

Atrenta’s Spring Cleaning Deal
by Paul McLellan on 04-16-2012 at 9:00 am

Atrenta is having a special offer to let you “spring clean” your IP for free. They are providing two weeks of free access to the Atrenta IP kit starting from today, April 16th, until the end of May. During this period, qualified design groups in the US will be able to use the kit for two consecutive weeks to “spring… Read More


High Yield and Performance – How to Assure?

High Yield and Performance – How to Assure?
by Pawan Fangaria on 04-16-2012 at 7:30 am

In today’s era, high performance mobile devices are asserting their place in every gizmos we play with and guess what enables them work efficiently behind the scene – it’s large chunks of memory with low power and high speed, packed as dense as possible. Ever growing requirement of power, performance and area led us to process nodes… Read More


Making your ARMs POP

Making your ARMs POP
by Paul McLellan on 04-16-2012 at 6:30 am

Just in time for TSMC’s technology symposium (tomorrow) ARM have announced a whole portfolio of new Processor Optimization Packs (POPs) for TSMC 40nm and 28nm. For most people, me included, my first question was ‘What is a POP?’

A POP is three things:

  • physical IP
  • certified benchmarking
  • implementation knowledge
Read More