Interview with David Tester VP of Engineering Mach42David Tester is the VP of Engineering at…Read More
The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node SurvivalThe philosophy of relying on a single, unified…Read More
CTO Interview with Taylor Barton of Certus SemiconductorTaylor Barton is a Lead Analog/Mixed-Signal and I/O…Read More
Generating Chip Subsystems Automatically: A New Answer to Manage Chip Design Complexity By Defacto Staff Today’s chips are no longer…Read More
Reimagining 3D IC Design: From Architecture to SignoffBy Keith Felton, Andras Vass-Varnai and Todd Burkholder,…Read More
I always enjoy attending the SystemC User group to see what is being done by users of SystemC. This time was no exception. Not only is it FREE, but the professional networking around the meeting, presentations, and break times are terrific.
There were 5 paper presentations at the North American SystemC User Group (NASCUG) on Monday,… Read More
This is a new brick that Synopsys brings to build FD-SOI credibility. We have talked at Semiwiki about FD-SOI technology developed by the LETI and STM, and recently endorsed by Samsung Foundry, offering a more than credible second source to STM. And we have said that the FD-SOI introduction will need to be supported by EDA and IP vendors… Read More
So what was the overall theme of DAC this year? Usually there seems to be some trend that is hot. A few years ago it was power, then more recently all the stuff associated with 20nm and 16nm such as FinFETs and double patterning. Those things are still around, of course, and there are new generations of tools.
One theme is that more design… Read More
You will not believe this, but the family was picking me up Friday evening from the airport and on the way home… Get this, for real, the wife asks me to cut her hair tomorrow. Now the three of you that read my stuff, know what happened before. I resisted, and firmly said ‘No’…The wife seeing my macho stance began appealing to my engineer’s… Read More
How much power does a system consume? The simplistic path to power estimation for a system used to be tossing a few metrics – standby, typical, worst case, with figures pulled from a datasheet, simulation, or physical measurement – into a spreadsheet. After filling the remaining holes with SWAG (scientific wild-ass guesses), … Read More
Tuesday morning at DAC I enjoyed a free breakfast courtesy of Synopsysand GLOBALFOUNDRIESwhere I learned more about the emerging market of IoT, and what it means to semiconductor, EDA and IP vendors. Panelists included: Semico Research, HP, Synopsys, GLOBALFOUNDRIES and Broadcom. … Read More
While focus of the semiconductor industry has shifted to DACin this week and unfortunately I couldn’t attend due to some of my management exams, in my spare time I was browsing through some of the webpages of Cadenceto check their new offerings (although they have a great list of items to showcase at DAC) and to my pleasure I came across… Read More
When I hear the phrase “high sigma” I think of the EDA vendor Solido, however at DAC on Monday I visited another EDA company called MunEDAthat has several products of interest to transistor-level IC designers. I was able to speak with three different people from MunEDA and here’s what I learned.… Read More
Synopsyshosted an AMS Luncheon panel today at DACin the Westin Hotel and invited four customers to talk about their actual design challenges and experiences. I’ve typed up my notes from this event.… Read More
First thing at DACtoday I met with Greg Lebsack of Tanner EDA to ask about what’s new in the past year for his EDA company. Here are my meeting notes, so there’s not much prose for my DAC blogs this year.
… Read More
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The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival