Breaking the Clock Lane Barrier: MIPI C-PHY/D-PHY Combo IP on TSMC N2PThe transition to advanced process nodes is reshaping…Read More
John Barr: The EDA Veteran and Award-Winning Needham Funds Portfolio ManagerJohn Barr, Portfolio Manager of the top-ranked Needham…Read More
Why Generic LLMs Fall Short for Critical Engineering DocumentationEngineering documentation has always been difficult to produce,…Read More
Re-Spins Get You Fired, Says Intel CEO Lip-Bu TanIntel CEO Lip-Bu Tan’s statement that “re-spins get…Read More
Caspia's AI Makes You a Security Verification ExpertLet’s face it, powerful, highly trained AI is…Read More
Migration to cloud computing for scientific and engineering applications is inevitable. More specifically for IC design, the benefits are significant:
Moore’s is still the law, and device scaling remains the key focus of front-end process research, however next-generation technologies–and the Big Data, cloud computing world that supports mobile, IoT, and other next-gen applications–are the new drivers, bringing new demands and challenges running … Read More
It really is quite a racket. Investor bloggers spread semiconductor disinformation for $.01 per click, that coincidentally covers their stock positions, and I get paid $300 per hour to explain it to Wall Street. While I appreciate the opportunity to bond with the financial people, I do wonder how these bloggers sleep at night.… Read More
I’ve worked with Solido for 5 years, and it’s been a pleasure to watch the world’s top semiconductor companies and foundries adopt Solido software for their SPICE simulation flows.
Sub-28nm design starts are accelerating, growing from 150 in 2012 to 900 this year. The move to sub-28nm design nodes is being driven by consumer electronic… Read More
There has been a lot of railing lately about how we don’t have quite the right chips for the upcoming wave of wearables. Chips one would drop in a smartphone are often overkill and overpowered, burning through electrons too quickly. Chips one would use for a simple control task generally lack peripherals and performance, offsetting… Read More
This is the third part of a series answering the most frequently asked questions I get from Wall Street. Please read the previous two articles on Intel’s Manufacturing Lead and Intel’s SoC Challenge before flaming me in the comment section. First let’s look at why there is a foundry business and go from there.
The big… Read More
Wait, didn’t Cadence just acquire Jasper. Why is there a Jasper at DAC post?
So the big event is lunch on Tuesday, on Treasure Island. For out of towners that is the island in the middle of the bay bridge (actually just half of it). Food trucks, awesome views of the bay, and really cool street performers. There will be street magic,… Read More
For the first time in DAC history there is an automotive track. Being a car person myself this is exciting news. I had a quick chat with Anne Cirkel, Vice Chair of DAC, and she sent me the following information to get us prepared for our week in San Francisco. The weather is going to be great so plan accordingly!
Ever increasing feature… Read More
The concept and use of virtual prototypes continues to grow each year in electronics design, mostly because it really does shorten product development cycles by allowing software engineers to start early debug and fix errors prior to production. Other useful benefits to virtual prototyping include software optimization, … Read More
Ever since I started talking about Virtual Fabrication I have mostly looked at it from the manufacturers’ perspective, where it has obvious benefits to develop and model new process technology. But what about the fabless design concept and indeed even the semiconductor IP world that has spawned from it as well? It seems that Virtual… Read More
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Intel: Pushing EMIB Forward: Design Methodology Insights with Synopsys Tools