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Pushing on AXI-connected IP in FPGAs

Pushing on AXI-connected IP in FPGAs
by Don Dingee on 11-03-2015 at 12:00 pm

Success stories are great. Reading how someone uses a product contributes much more insight than reading about a product. Last month we had a teaser for a presentation by Wave Semiconductor; this month, we have the slides showing how they are using FPGA-based prototyping, AXI transactions, and DPI to speed up development.

First,… Read More


Perfecting the Great Verification Fugue

Perfecting the Great Verification Fugue
by Bernard Murphy on 11-03-2015 at 7:00 am

Michael Sanie (Senior Director Marketing in the Synopsys Verification Group) gave the wrap-up presentation at SpyGlass World recently, on the Synopsys Verification Direction. I learned from an interview Michael gave to Paul McLellan that he is an accomplished pianist. I’m a pianist also, though of considerably less talent,… Read More


Implications of LTE in the 5 GHz Band

Implications of LTE in the 5 GHz Band
by Maury Wood on 11-02-2015 at 4:00 pm

Back in December 2013, during a 3GPP Radio Access Network (RAN) plenary meeting, Ericsson and Qualcomm introduced LTE-Unlicensed, a scheme that puts LTE-Advanced signals in the 5 GHz unlicensed UNII band, in conjunction with an LTE “anchor” signal in a licensed band. The objective is supplemental downlink bandwidth… Read More


How Magwel is Tapping Tried and True Business Strategy in Targeting ESD

How Magwel is Tapping Tried and True Business Strategy in Targeting ESD
by Tom Simon on 11-02-2015 at 12:00 pm

Often when a company starts out it takes a while for it to find the sweet spot in the marketplace. Very often it is feedback from existing customers and business success that can help point the way for small companies as they grow. This is just as true in EDA as it is in retailing or consumer products. For instance, Mentor Graphics, though… Read More


Verification with Tcl for what?

Verification with Tcl for what?
by Anatoly Myshkin on 11-02-2015 at 7:00 am

Nowadays, verification as one of the most complex SoC, FPGA, and ASIC development flow stages always requires new approaches. The following is an introduction to TcL vs/ with SystemVerilog and VHDL, the first in a 3 part series. Part 2 will be “Tcl vs Python, Bluespec” and part 3 will be “VerTcl description”.… Read More


Silicon Valley USPTO is Open for Business!

Silicon Valley USPTO is Open for Business!
by Daniel Nenni on 11-01-2015 at 4:00 pm

Probably the best and most attended EDAC Emerging Companies event happened last week so congratulations to Bob Smith and staff. The premise was to develop, strengthen, and protect your intellectual property which is paramount to all emerging technology companies. Many people in this industry, including myself, have learned… Read More


Moving with Purpose for Certainty

Moving with Purpose for Certainty
by Pawan Fangaria on 11-01-2015 at 12:00 pm

In 1492 Christopher Columbus sailed from Spain towards west on Atlantic Ocean in search of Asia and Indies. Between his four voyages (1492 – 1502) he discovered many different islands and then what we call Americas. Although he had a compass with him, imagine searching a needle in a haystack. Even with localization of areas and then… Read More


How to Live with Rapid Changes During Early Development of IP

How to Live with Rapid Changes During Early Development of IP
by Tom Simon on 10-30-2015 at 4:00 pm

Best practices call for using a version control system with systematic releases when developing IP. However, in the early stages of IP development using a rigid version control system with a cumbersome release process can hinder productivity. To fully understand how this works we should start by defining what is meant when we … Read More