American television viewers of a certain age will remember the Carol Burnett Show and its star, Carol Burnett, and her customary ear tug at the end of each show. TV Guide tells us the “ear tug first made famous during the 1967-79 run of CBS’s Carol Burnett Show was a message to her grandmother, a way of saying, “Hello,… Read More
WEBINAR: Revolutionizing Electrical Verification in IC DesignIn the complex world of IC design, electrical…Read More
Hierarchically defining bump and pin regions overcomes 3D IC complexityBy Todd Burkholder and Per Viklund, Siemens EDA…Read More
CDC Verification for Safety-Critical Designs – What You Need to KnowVerification is always a top priority for any…Read More
Ceva Unleashes Wi-Fi 7 Pulse: Awakening Instant AI Brains in IoT and Physical RobotsIn the rapidly evolving landscape of connected devices,…Read More
Adding Expertise to GenAI: An Insightful Study on Fine-TuningI wrote earlier about how deep expertise, say…Read More
Webinar from CEVA: Machine Type Communication
By 2020, ABI Research predicts that there will be more than 45 billion connected devices worldwide. More than half of these devices will incorporate multiple standards in the same device, such as Wi-Fi, 802.15.4g, GNSS and cellular communications.
This webinar will address the question: How To Design a LTE-Based M2M Asset Tracker… Read More
How China can Lead in the Semiconductor Industry
Since a few years China has been very aggressive in acquiring semiconductor companies around the world. Last year, Chinese government along with PE (Private Equity) and other investors in China announced an ambitious plan under which more than $150 billion were to be invested over next 5 to 10 years in developing semiconductor… Read More
Ajoy – History, Perspectives and Crossing the Chasm
EDAC hosted an event at DVCon this week where Jim Hogan interviewed Ajoy Bose (CEO of Atrenta prior to its acquisition by Synopsys). The nominal purpose was to talk about turning a venture into a valuable enterprise. This was covered but, in Jim’s way, it was really a more wide-ranging and personal interview. This is an abstract of… Read More
IC Design and OpenAccess
EDA vendors have long used proprietary file and database formats to keep their users locked into their specific tool flow and keep any competitors from sharing in the IC design process. Along the way the actual users of EDA tools have often requested and helped to create interoperable flows so that they could mix and match multiple… Read More
Dr. Walden Rhines on the Past Present and Future!
Who can present seventy six slides in sixty minutes, still have time for questions, AND make it interesting? Dr. Walden Rhines that’s who. Here is a link to the presentation but I have to warn you, it is a 100MB PDF file:
Design Verification Challenges: Past, Present, and Future
The DVCon conference was well attended again this year… Read More
My Last Day at Fairchild
Well today is the day. I am officially retired from Fairchild after 36 years and 9 months on the job. I have worked for Fairchild Camera and Instrument, Fairchild a Schlumberger Company, National Semiconductor and Fairchild Semiconductor. It’s been everything I was hoping for and more. By the way, I walked out the front door… Read More
3 IoT demos highlight Atmel SAMA5
At the high end of the Atmel product spectrum resides SAMA5 based on an ARM Cortex-A5 core. With an MMU supporting Linux or Android, plus on-the-fly memory encryption and ARM TrustZone in some variants, the SAMA5 family is drawing interest from IoT app developers. We’ll look at three examples, all illustrating how important seamless… Read More
Start Your HBM 2.5D Design Today!
Next week there is a live seminar at the famed Computer Museum in Silicon Valley that you won’t want to miss. If you haven’t been to the Computer Museum here is what you are missing:… Read More
A Brief History of Defacto Technologies
In early 2000s, semiconductor design at RTL level was gaining momentum. The idea was to process more design steps such as insertion of test and other design structures upfront at the RTL level. The design optimization and verification were to be done at the RTL level to reduce long iterations through gate level design because changes… Read More
AI RTL Generation versus AI RTL Verification