Let’s face it, designs are getting harder, much harder. Gone are the days when the electrical and mechanical design of a system occurred separately. Maybe ten years ago this practice was acceptable. Once the electrical design was completed (either the chip or the board) the parameters associated with the design were then given… Read More
Will Chiplet Adoption Mimic IP Adoption?
If we look at the semiconductor industry expansion during the last 25 years, adoption of design IP in every application appears to be one of the major factors of success, with silicon technology incredible development by a x100 factor, from 250nm in 2018 to 3nm (if not 2nm) in 2023. We foresee the move to chiplet-based architecture… Read More
Fail-Safe Electronics For Automotive
The automotive industry is on the brink of a revolutionary transformation, where predictive maintenance and monitoring are taking center stage. In a recent webinar panel session, industry experts delved into the challenges, current approaches, and future innovations surrounding the guarantee and extension of mission profiles.… Read More
Information Flow Tracking at RTL. Innovation in Verification
Explicit and implicit sneak paths to leak or compromise information continue to represent a threat to security. This paper looks a refinement of existing gate level information flow tracking (IFT) techniques extended to RTL, encouraging early-stage security optimization. Paul Cunningham (Senior VP/GM, Verification at … Read More
Making UVM faster through a new configuration system
The Universal Verification Methodology (UVM) is a popular way to help verify SystemVerilog designs, and it includes a configuration system that unfortunately has some speed and usage issues. Rich Edelman from Siemens EDA wrote a detailed 20-page paper on the topic of how to avoid these issues, and I’ve gone through it to… Read More
SPIE 2023 Buzz – Siemens Aims to Break Down Innovation Barriers by Extending Design Technology Co-Optimization
Preventing the propagation of systematic defects in today’s semiconductor design-to-fabrication process requires many validation, analysis and optimization steps. Tools involved in this process can include design rule checking (DRC), optical proximity correction (OPC) verification, mask writing and wafer printing… Read More
Application-Specific Lithography: Sense Amplifier and Sub-Wordline Driver Metal Patterning in DRAM
On a DRAM chip, the patterning of features outside the cell array can be just as challenging as those within the array itself. While the array contains features which are the most densely packed, at least they are regularly arranged. On the other hand, outside the array, the regularity is lost, but the in the most difficult cases, … Read More
Preventing SOC Schedule Delays Using the Cloud
In my previous article, we touched on ways to pull in the schedule. This time I’d like to analyze how peak usage affects project timeline and cost. The above graph is based on real pattern taken from one development week in Annapurna Labs 5nm Graviton.
The Graph shows the number of variable servers per hour per day. There’s a baseline… Read More
Is Intel cornering the market in ASML High NA tools? Not repeating EUV mistake
- Reports suggest Intel will get 6 of 10 ASML High NA tools in 2024
- Would give Intel a huge head start over TSMC & Samsung
- A big gamble but a potentially huge pay off
- Does this mean $4B in High NA tool sales for ASML in 2024?
News suggests Intel will get 6 of first 10 High NA tools made by ASML in 2024
An industry news source, Trendforce, reports… Read More
Podcast EP199: How Rambus is Helping to Counter the Security Threats of Quantum Computing with Scott Best
Dan is joined by Scott Best, technical director at Rambus. His research areas are memory architectures, 3D packaging, and security processors. Scott joined Rambus in 1998 and has served in many and varied technical roles. He has become one of the most prolific inventors in the company’s history. Over the course of his career at … Read More
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