Got a great idea for a device with AI at the extreme edge? Self-contained and can run on a coin cell battery, maybe even harvested energy? Needs to fit in a space not much larger than a quarter? Eta Compute has a board for you. This comes with 2 MEMS microphones, a pressure/temperature sensor, a 6-axis MEMS accelerometer/gyroscope,… Read More
The 71st International Electron Devices Meeting (IEDM 2025)It is hard to believe this conference is…Read More
TSMC’s 2026 AZ Exclusive Experience Day: Bridging Careers and Semiconductor InnovationIn February of 2026, Taiwan Semiconductor Manufacturing Company…Read More
DAC – The Chips to Systems Conference 2026The Design Automation Chips to Systems Conference is…Read More
Taming Advanced Node Clock Network Challenges: JitterClock jitter rarely fails in obvious ways. In…Read MoreAchronix Blog Roundup!
Blogging is not an easy thing to do. It takes time, patience, commitment, and creativity. SemiWiki brought blogging to the semiconductor industry and many companies have followed. Very few have been successful with personal or corporate blogs but as a premier semiconductor blogger I have developed a proven recipe over the last… Read More
Interface IP Category to Overtake CPU IP by 2025?
The Interface Design IP market explodes, growing by 18% in 2019, with $870 million, when CPU IP category grew by 5% at $1,460 million. In fact, Interface IP market is forecasted to sustain high growth rate for the next five years, as calculated by IPnest in the “Interface IP Survey 2015-2019 & Forecast 2020-2024”, to reach $1,800… Read More
Arm Rings the Bell in Supercomputing
Late last year I wrote about Arm’s efforts to play a role in servers, in AWS, and particularly Arm-based supercomputing, in the Sandia Astra roadmap and in partnering with NVIDIA who are in the Oak Ridge Summit supercomputer. These steps came, at least for me, with an implicit “Good for them, playing a role on the edges of these challenging… Read More
Siemens Acquires UltraSoC to Drive Design for Silicon Lifecycle Management
As reported recently by Dan Nenni, Siemens has signed an agreement to acquire Cambridge, UK-based UltraSoC Technologies Ltd. We’ve all seen plenty of mergers and acquisitions in EDA. Some transactions perform better than others. The best ones enhance an existing product or service by blending non-overlapping technologies.… Read More
Waking Up to the Requirements of Voice Activity Detection
There is a famous scene in the 1976 movie Taxi Driver when Robert De Niro’s character Travis is pretending to have a conversation looking in the mirror and repeatedly saying “Are you talking to me?”. I think about this scene every time I use a voice active device – Hey, are you talking to me? Yes, I am, but are you listening?
Voice command,… Read More
The Future of Chip Design with the Cadence iSpatial Flow
A few months ago, I wrote about the announcement of a new digital full flow from Cadence. In that piece, I focused on the machine learning (ML) aspects of the new tool. I had covered a discussion with Cadence’s Paul Cunningham a week before that explored ML in Cadence products, so it was timely to dive into a real-world example of the … Read More
A Compelling Application for AI in Semiconductor Manufacturing
There have been a multitude of announcements recently relative to the incorporation of machine learning (ML) methods into EDA tool algorithms, mostly in the physical implementation flows. For example, deterministic ML-based decision algorithms applied to cell placement and signal interconnect routing promise to expedite… Read More
Teaching AI to be Evil with Unethical Data
An Artificial Intelligence (AI) system is only as good as its training. For AI Machine Learning (ML) and Deep Learning (DL) frameworks, the training data sets are a crucial element that defines how the system will operate. Feed it skewed or biased information and it will create a flawed inference engine.
Application-Specific Lithography: The 5nm 6-Track Cell
An update is now available here: Application-Specific Lithography: Patterning 5nm 5.5-Track Metal by DUV
The 5nm foundry (e.g., TSMC) node may see the introduction of 6-track cells (two double-width rails plus four minimum-width dense lines) with a minimum metal pitch in the neighborhood of 30 nm. IMEC had studied a representative… Read More



The Risk of Not Optimizing Clock Power