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Semico Research Quantifies the Business Impact of Deep Data Analytics, Concludes It Accelerates SoC TTM by Six Months

Semico Research Quantifies the Business Impact of Deep Data Analytics, Concludes It Accelerates SoC TTM by Six Months
by Kalar Rajendiran on 06-14-2023 at 10:00 am

Design Costs Comparison

The semiconductor industry has been responding to increasing device complexity and performance requirements in multiple ways. To create smaller and more densely packed components, the industry is continually advancing manufacturing technology. This includes the use of new materials and processes, such as extreme ultraviolet… Read More


TSMC Doubles Down on Semiconductor Packaging!

TSMC Doubles Down on Semiconductor Packaging!
by Daniel Nenni on 06-14-2023 at 6:00 am

TSMC 3DFabric Integration

Last week TSMC announced the opening of an advanced backend fab for the expansion of the TSMC 3DFabric System Integration Technology. It’s a significant announcement as the chip packaging arms race with Intel and Samsung is heating up.

Fab 6 is TSMC’s first all-in-one advanced packaging and testing fab which is part of the… Read More


The Opportunity Costs of using foundry I/O vs. high-performance custom I/O Libraries

The Opportunity Costs of using foundry I/O vs. high-performance custom I/O Libraries
by Stephen Fairbanks on 06-13-2023 at 10:00 am

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The original vision for Certus Semiconductor in 2008 was to leverage production I/O Libraries from more significant partners, starting with Freescale, and take it to smaller external customers for licensing.  This IP was proven and validated, with an excellent silicon track record and big company support; in our minds, we thought,… Read More


WEBINAR: Revolutionizing Chip Design with 2.5D/3D-IC Design Technology

WEBINAR: Revolutionizing Chip Design with 2.5D/3D-IC Design Technology
by Daniel Nenni on 06-12-2023 at 10:00 am

Figure 1 (2)

In the 3D-IC (Three-dimensional integrated circuit) chip design method, chiplets or wafers are stacked vertically on top of each other and are connected using Through Silicon Vias (TSVs) or hybrid bonding.

The 2.5D-IC design method places multiple chiplets alongside each other on a silicon interposer. Microbumps and interconnect… Read More


VLSI Symposium – Intel PowerVia Technology

VLSI Symposium – Intel PowerVia Technology
by Scotten Jones on 06-12-2023 at 6:00 am

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At the 2023 VLSI Symposium on Technology and Circuits, Intel presented two papers on their PowerVia technology. We received a pre-conference briefing on the technology embargoed until the conference began and received the papers.

Traditionally all interconnects have taken place on the front side of devices with signal and … Read More


Podcast EP167: What is Dirty Data and How yieldHUB Helps Fix It With Carl Moore

Podcast EP167: What is Dirty Data and How yieldHUB Helps Fix It With Carl Moore
by Daniel Nenni on 06-09-2023 at 10:00 am

Dan is joined by Carl Moore, a Yield Management Specialist at yieldHUB. Carl is a semiconductor and yield management expert with more than 35 years of experience in the industry. Carl has held technical management positions across product and test engineering, assembly, manufacturing, and design.

Carl explains what “dirty… Read More


CEO Interview: Dr. Sean Wei of Easy-Logic

CEO Interview: Dr. Sean Wei of Easy-Logic
by Daniel Nenni on 06-09-2023 at 6:00 am

Photo Sean Wei 006

Dr. Wei has served as CEO & CTO of Easy-Logic since 2020.  Prior to this role, Dr. Wei served as CTO since 2014 where he constructed the core algorithm and the tool structure of EasyECO.  As the CEO, Dr. Wei focuses on building a strong company infrastructure.  In his CTO role he interfaces with strategic ASIC design customers … Read More


Getting the most out of a shift-left IC physical verification flow with the Calibre nmPlatform

Getting the most out of a shift-left IC physical verification flow with the Calibre nmPlatform
by Peter Bennet on 06-08-2023 at 10:00 am

Correct Verify Debug

Who first came up with this term shift-left ? I’d assumed Siemens EDA as they use it so widely. But their latest white paper on the productivity improvements possible with shift-left Calibre IC verification flows puts the record straight: a software engineer called Larry Smith bagged the naming rights in a 2001 paper (leapfrogging… Read More


Democratizing the Ultimate Audio Experience

Democratizing the Ultimate Audio Experience
by Bernard Murphy on 06-08-2023 at 6:00 am

3D Audio

I enjoy talking with CEVA because they work on such interesting consumer products (among other product lines). My most recent discussion was with Seth Sternberg (Sensors and Audio software at CEVA), on spatial or 3D audio. The first steps to a somewhat immersive audio experience were stereo and surround sound, placing sound sources… Read More


Nominations for Phil Kaufman Award, Phil Kaufman Hall of Fame Close June 30

Nominations for Phil Kaufman Award, Phil Kaufman Hall of Fame Close June 30
by Paul Cohen on 06-07-2023 at 10:00 am

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Plan ahead now because Friday, June 30, is the deadline to submit nominations for the Phil Kaufman Award and the Phil Kaufman Hall of Fame for anyone you think is deserving of these honors. If you haven’t given it any thought, please consider nominating someone.

Before we look at both and the nomination requirements, here’s a thumbnail… Read More