EUV has long been an interesting story. We have written 200+ articles on EUV and they just keep on coming. Thankfully the premier lithography conference is right here in Silicon Valley. SPIE began in 1955 as the Society of Photographic Instrumentation Engineers, bringing together engineers using scientific cameras and high-speed… Read More
CTO Interview with Taylor Barton of Certus SemiconductorTaylor Barton is a Lead Analog/Mixed-Signal and I/O…Read More
Generating Chip Subsystems Automatically: A New Answer to Manage Chip Design Complexity By Defacto Staff Today’s chips are no longer…Read More
Reimagining 3D IC Design: From Architecture to SignoffBy Keith Felton, Andras Vass-Varnai and Todd Burkholder,…Read More
GSA Honors Sanjay Mehrotra as Memory Takes Center Stage in ComputingThe Global Semiconductor Alliance will present Micron Technology…Read More
NIST Sets a Clearer Course for the Post-Quantum Security TransitionNIST’s report, Transition to Post-Quantum Cryptography Standards, gives…Read MorePodcast EP373: The Impact of yieldHUB Live and Details of Upcoming Show Participation with Gillian O’Donnell
Daniel is joined by Gillian O’Donnell, Director of Growth at yieldHUB, the enterprise yield management platform trusted by semiconductor and photonics manufacturers worldwide. She leads business development, marketing, PR, and partnerships, with a particular focus on yieldHUB Live, the company’s real-time… Read More
CEO Interview with Alex Higginbottom of Zenithon
Alex Higginbottom is co-founder and CEO of Zenithon, which he started with Abetharan Antony in July 2025 to build the first world models for extreme physics. He previously worked in deeptech commercialisation and spent time in fusion research, starting a PhD in the field before leaving after a year to build the company.
Tell … Read More
From 25 Million Pixels to a Six-Ounce Product: Engineering Visor for Manufacturing
By Dr. Moh Kolbehdari
Putting roughly 25 million pixels into a wearable device weighing about six ounces sounds, at first, like a display problem.
It is not.
The displays must fit behind an optical system capable of turning those pixels into a usable visual field. Compute must generate and move the required data. Power must support… Read More
TSMC 2026 OIP Ecosystem Forum Summary
TSMC’s 2026 Open Innovation Platform Forum presented artificial intelligence as the force reshaping semiconductor design. Its central argument is that faster chips will require progress across the whole system: logic, memory, packaging, interconnects, power delivery and design methods. TSMC places its partner ecosystem… Read More
CASPA CEO Summit and Why it Matters
It’s an honor to attend events like this as a guest, and even more so as a speaker. On Friday at 3:30 p.m., I’ll be moderating a panel with the CEOs of three of the hottest AI startups. I definitely have a few questions ready for them! My beautiful wife and I will also be at the banquet. I hope to see you there!
The CASPA CEO Summit arrives … Read More
CEO Interview with Lieuwke de Jong of Sweet Atoms
Lieuwke de Jong is a globally experienced executive and entrepreneur who operates at the intersection of industry, government and innovation. His career spans defense-aligned sectors, aerospace, energy, life sciences and advanced materials and he is known for connecting stakeholders across government, research and industry… Read More
Data Center Energy Trends Force a Rethink of Chip Power Delivery
Intel Foundry published a two article series on chip power delivery that are worth reading. Here is a quick summary:
Artificial intelligence is changing the requirements for semiconductor innovation. Faster transistors and denser packaging remain essential, but their benefits increasingly depend on another engineering… Read More
WEBINAR: The Convergence of Edge Accelerators
The rapid growth of AI at the edge is forcing SoC architects to rethink traditional processor designs. Dedicated NPUs deliver impressive performance for today’s models, but evolving AI workloads, increasing system complexity and growing pressure on power and silicon budgets are exposing the limitations of fixed-function… Read More
The silent killer of analog reliability: Why SPICE misses floating net
By Bhanu Pandey
The semiconductor industry is currently facing a significant challenge in functional verification. According to the most recent Wilson Research Group / Siemens EDA Functional Verification Study, first-silicon success rates have hit a historic low, with nearly 68% of designs requiring two or more spins. While… Read More


The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival