Efficient Bump and TSV Planning for Multi-Die Chip DesignsThe semiconductor industry has experienced rapid advancements in…Read More
The Evolution of RISC-V and the Role of Andes Technology in Building a Global EcosystemDuring my frequent trips to Taiwan as a…Read More
Capability Hardware Enhanced RISC Instructions CHERI AllianceThe CHERI Alliance is a non-profit organization dedicated…Read More
Operationalizing Secure Semiconductor Collaboration: Safely, Globally, and at ScaleSemiconductor manufacturing is among the most complex industrial…Read More
Keynote: On-Package Chiplet Innovations with UCIeIn the rapidly evolving landscape of semiconductor technology,…Read More
The semiconductor analysts are at it again, revising numbers, polishing their guesstimates, and patting each other on the back for being equally as inaccurate. I blame these crystal ball hacks for the semiconductor shortages and price hikes we are experiencing today.
These people get paid to guide investors, and the industry… Read More
A venture capitalist offered the advice, “Startup investors are attracted by good people making a good product for a growing market.” That wisdom, as much as any served as the foundation for the company Mentor Graphics would become.… Read More
Again, my economic bellwether is TSMC, and judging by the first half, 2010 will go down as one of the most profitable years the semiconductor industry has ever seen. In the 2[SUP]nd[/SUP] quarter the foundries again posted record breaking wafer shipments, revenues, and profits. 3[SUP]rd[/SUP] quarter foundry financials should… Read More
When TSMC and Mentor Graphics held a joint seminar for mutual customers to go over new DFM requirements at 45/40 nm, two customers basically asked the same question, “What do you mean by mandatory?” Of course, TSMC wasn’t going to stand over them and say, “Mandatory means mandatory, what part of mandatory don’t you understand?” … Read More
When TSMC and Mentor Graphics held a joint seminar for mutual customers to go over new DFM requirements at 45/40 nm, two customers basically asked the same question, “What do you mean by mandatory?” Of course, TSMC wasn’t going to stand over them and say, “Mandatory means mandatory, what part of mandatory don’t you understand?” … Read More
What I’m really describing here is an over-simplified backend flow for physical design of low power ICs with multiple voltage domains. If you haven’t ventured into this territory yet, this will hopefully give you some food for thought. Here are the basic steps:… Read More
Clock designers are an enigma. Clock designers in general are die hard Star Wars fans, own vintage Porsches that leak oil by the gallon, usually have lava lamps in their offices/cubicles, wear fancy leather jackets in the peak of summer, and have like-minded clock designers as best lunch buddies. … Read More
Resistance is futile. I recently caved and switched to an iPhone after having been a loyal Google phone user for more than year. Apart from the coolness factor, my main motivation was corporate mail support that was absent in Gphone, plus the fact that I got the iPhone for free when my wife upgraded hers. The difference is day and night… Read More
What I’m really describing here is an over-simplified backend flow for physical design of low power ICs with multiple voltage domains. If you haven’t ventured into this territory yet, this will hopefully give you some food for thought. Here are the basic steps:… Read More
In my submission about TSMC making some DFM analysis steps mandatory at 45nm (see “TSMC’s DFM Announcement”), I ended with a question about why the foundries can’t just write better design rules (and rule decks) to make sure all designs yield well. Here’s my take on this complicated question.… Read More
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Things From Intel 10K That Make You Go …. Hmmmm